196 lines
6.9 KiB
C
196 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef CMDQ_EVENT_COMMON
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#define CMDQ_EVENT_COMMON
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/* Define CMDQ events
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*
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* For hardware event must define in device tree.
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* For SW event assign event ID here directly.
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*
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* Note: event name must sync to cmdq_events table in mdp_event_common.c
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*/
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enum cmdq_event {
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/* MDP start frame */
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CMDQ_EVENT_MDP_RDMA0_SOF, /* 0 */
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CMDQ_EVENT_MDP_RDMA1_SOF, /* 1 */
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CMDQ_EVENT_MDP_RDMA2_SOF, /* 2 */
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CMDQ_EVENT_MDP_RDMA3_SOF, /* 3 */
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CMDQ_EVENT_MDP_RSZ0_SOF, /* 4 */
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CMDQ_EVENT_MDP_RSZ1_SOF, /* 5 */
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CMDQ_EVENT_MDP_RSZ2_SOF, /* 6 */
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CMDQ_EVENT_MDP_RSZ3_SOF, /* 7 */
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CMDQ_EVENT_MDP_TDSHP_SOF, /* 8 */
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CMDQ_EVENT_MDP_TDSHP1_SOF, /* 9 */
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CMDQ_EVENT_MDP_TDSHP2_SOF, /* 10 */
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CMDQ_EVENT_MDP_TDSHP3_SOF, /* 11 */
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CMDQ_EVENT_MDP_WDMA_SOF, /* 12 */
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CMDQ_EVENT_MDP_WROT_SOF, /* 13 */
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CMDQ_EVENT_MDP_WROT0_SOF, /* 14 */
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CMDQ_EVENT_MDP_WROT1_SOF, /* 15 */
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CMDQ_EVENT_MDP_WROT2_SOF, /* 16 */
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CMDQ_EVENT_MDP_WROT3_SOF, /* 17 */
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/* Display start frame */
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CMDQ_EVENT_DISP_RDMA0_SOF, /* 18 */
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/* MDP frame done */
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CMDQ_EVENT_MDP_RDMA0_EOF, /* 19 */
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CMDQ_EVENT_MDP_RDMA1_EOF, /* 20 */
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CMDQ_EVENT_MDP_RDMA2_EOF, /* 21 */
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CMDQ_EVENT_MDP_RDMA3_EOF, /* 22 */
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CMDQ_EVENT_MDP_RSZ0_EOF, /* 23 */
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CMDQ_EVENT_MDP_RSZ1_EOF, /* 24 */
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CMDQ_EVENT_MDP_RSZ2_EOF, /* 25 */
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CMDQ_EVENT_MDP_RSZ3_EOF, /* 26 */
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CMDQ_EVENT_MDP_TDSHP_EOF, /* 27 */
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CMDQ_EVENT_MDP_TDSHP1_EOF, /* 28 */
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CMDQ_EVENT_MDP_TDSHP2_EOF, /* 29 */
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CMDQ_EVENT_MDP_TDSHP3_EOF, /* 30 */
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CMDQ_EVENT_MDP_WDMA_EOF, /* 31 */
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CMDQ_EVENT_MDP_WROT_WRITE_EOF, /* 32 */
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CMDQ_EVENT_MDP_WROT0_WRITE_EOF, /* 33 */
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CMDQ_EVENT_MDP_WROT1_WRITE_EOF, /* 34 */
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CMDQ_EVENT_MDP_WROT2_WRITE_EOF, /* 35 */
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CMDQ_EVENT_MDP_WROT3_WRITE_EOF, /* 36 */
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/* Display frame done */
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CMDQ_EVENT_DISP_OVL0_EOF, /* 37 */
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CMDQ_EVENT_DISP_RDMA0_EOF, /* 38 */
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CMDQ_EVENT_DISP_WDMA0_EOF, /* 39 */
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/* ISP frame done */
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CMDQ_EVENT_ISP_PASS2_2_EOF, /* 40 */
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CMDQ_EVENT_ISP_PASS2_1_EOF, /* 41 */
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CMDQ_EVENT_ISP_PASS2_0_EOF, /* 42 */
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/* ISP (IMGSYS) frame done */
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CMDQ_EVENT_DIP_CQ_THREAD0_EOF, /* 43 */
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CMDQ_EVENT_DIP_CQ_THREAD1_EOF, /* 44 */
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CMDQ_EVENT_DIP_CQ_THREAD2_EOF, /* 45 */
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CMDQ_EVENT_DIP_CQ_THREAD3_EOF, /* 46 */
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CMDQ_EVENT_DIP_CQ_THREAD4_EOF, /* 47 */
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CMDQ_EVENT_DIP_CQ_THREAD5_EOF, /* 48 */
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CMDQ_EVENT_DIP_CQ_THREAD6_EOF, /* 49 */
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CMDQ_EVENT_DIP_CQ_THREAD7_EOF, /* 50 */
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CMDQ_EVENT_DIP_CQ_THREAD8_EOF, /* 51 */
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CMDQ_EVENT_DIP_CQ_THREAD9_EOF, /* 52 */
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CMDQ_EVENT_DIP_CQ_THREAD10_EOF, /* 53 */
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CMDQ_EVENT_DIP_CQ_THREAD11_EOF, /* 54 */
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CMDQ_EVENT_DIP_CQ_THREAD12_EOF, /* 55 */
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CMDQ_EVENT_DIP_CQ_THREAD13_EOF, /* 56 */
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CMDQ_EVENT_DIP_CQ_THREAD14_EOF, /* 57 */
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CMDQ_EVENT_DIP_CQ_THREAD15_EOF, /* 58 */
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CMDQ_EVENT_DIP_CQ_THREAD16_EOF, /* 59 */
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CMDQ_EVENT_DIP_CQ_THREAD17_EOF, /* 60 */
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CMDQ_EVENT_DIP_CQ_THREAD18_EOF, /* 61 */
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/* JPEG frame done */
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CMDQ_EVENT_JPEG_ENC_EOF, /* 62 */
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CMDQ_EVENT_JPEG_DEC_EOF, /* 63 */
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/* WPE frame done */
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CMDQ_EVENT_WPE_A_EOF, /* 64 */
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CMDQ_EVENT_WPE_B_FRAME_DONE, /* 65 */
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/* Direct-link start frame */
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CMDQ_EVENT_IMG_DL_RELAY_SOF, /* 66 */
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CMDQ_EVENT_IMG_DL_RELAY1_SOF, /* 67 */
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CMDQ_EVENT_IMG_DL_RELAY2_SOF, /* 68 */
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CMDQ_EVENT_IMG_DL_RELAY3_SOF, /* 69 */
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/* Dual DIP frame done */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_0, /* 70 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_1, /* 71 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_2, /* 72 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_3, /* 73 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_4, /* 74 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_5, /* 75 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_6, /* 76 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_7, /* 77 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_8, /* 78 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_9, /* 79 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_10, /* 80 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_11, /* 81 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_12, /* 82 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_13, /* 83 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_14, /* 84 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_15, /* 85 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_16, /* 86 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_17, /* 87 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_18, /* 88 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_19, /* 89 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_20, /* 90 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_21, /* 91 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_22, /* 92 */
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CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_23, /* 93 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_0, /* 94 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_1, /* 95 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_2, /* 96 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_3, /* 97 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_4, /* 98 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_5, /* 99 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_6, /* 100 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_7, /* 101 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_8, /* 102 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_9, /* 103 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_10, /* 104 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_11, /* 105 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_12, /* 106 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_13, /* 107 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_14, /* 108 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_15, /* 109 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_16, /* 110 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_17, /* 111 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_18, /* 112 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_19, /* 113 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_20, /* 114 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_21, /* 115 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_22, /* 116 */
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CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_23, /* 117 */
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/* Keep this at the end of HW events */
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CMDQ_MAX_HW_EVENT_COUNT = 512,
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/* token 512 to 639 may set secure */
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/* SW Sync Tokens (Pre-defined) */
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/* Pass-2 notifies VENC frame is ready to be encoded */
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CMDQ_SYNC_TOKEN_VENC_INPUT_READY = 645, /* 645 */
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/* VENC notifies Pass-2 encode done so next frame may start */
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CMDQ_SYNC_TOKEN_VENC_EOF, /* 646 */
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/* SW Sync Tokens (User-defined) */
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CMDQ_SYNC_TOKEN_USER_0 = 649, /* 649 */
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CMDQ_SYNC_TOKEN_USER_1, /* 650 */
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/* isp */
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CMDQ_SYNC_TOKEN_MSS = 665, /* 665 */
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CMDQ_SYNC_TOKEN_MSF, /* 666 */
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/* token after 700 sync user space header */
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/* GPR access tokens (for HW register backup)
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* There are 15 32-bit GPR, 3 GPR form a set
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* (64-bit for address, 32-bit for value)
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*/
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CMDQ_SYNC_TOKEN_GPR_SET_0 = 700,
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CMDQ_SYNC_TOKEN_GPR_SET_1, /* 701 */
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CMDQ_SYNC_TOKEN_GPR_SET_2, /* 702 */
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CMDQ_SYNC_TOKEN_GPR_SET_3, /* 703 */
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CMDQ_SYNC_TOKEN_GPR_SET_4, /* 704 */
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/* Resource lock event to control resource in GCE thread */
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CMDQ_SYNC_RESOURCE_WROT0 = 710,
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CMDQ_SYNC_RESOURCE_WROT1 = 711,
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/* event id is 10 bit */
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CMDQ_SYNC_TOKEN_MAX = 0x3FF,
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CMDQ_SYNC_TOKEN_INVALID = -1,
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};
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#endif
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