108 lines
3 KiB
C
108 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MDP_BASE_H__
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#define __MDP_BASE_H__
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#define MDP_HW_CHECK
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#include "mach/mt_iommu.h"
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static u32 mdp_engine_port[ENGBASE_COUNT] = {
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0, // ENGBASE_MMSYS_CONFIG,
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M4U_PORT_L2_MDP_RDMA0, // ENGBASE_MDP_RDMA0,
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M4U_PORT_L3_MDP_RDMA1, // ENGBASE_MDP_RDMA1,
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M4U_PORT_L2_MDP_RDMA2, // ENGBASE_MDP_RDMA2,
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M4U_PORT_L3_MDP_RDMA3, // ENGBASE_MDP_RDMA3,
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0, // ENGBASE_MDP_FG0,
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0, // ENGBASE_MDP_FG1,
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0, // ENGBASE_MDP_AAL0,
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0, // ENGBASE_MDP_AAL1,
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0, // ENGBASE_MDP_AAL2,
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0, // ENGBASE_MDP_AAL3,
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0, // ENGBASE_MDP_HDR0,
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0, // ENGBASE_MDP_HDR1,
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0, // ENGBASE_MDP_RSZ0,
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0, // ENGBASE_MDP_RSZ1,
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0, // ENGBASE_MDP_RSZ2,
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0, // ENGBASE_MDP_RSZ3,
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M4U_PORT_L2_MDP_WROT0, // ENGBASE_MDP_WROT0,
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M4U_PORT_L3_MDP_WROT1, // ENGBASE_MDP_WROT1,
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M4U_PORT_L2_MDP_WROT2, // ENGBASE_MDP_WROT2,
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M4U_PORT_L3_MDP_WROT3, // ENGBASE_MDP_WROT3,
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0, // ENGBASE_MDP_TDSHP0,
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0, // ENGBASE_MDP_TDSHP1,
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0, // ENGBASE_MDP_TDSHP2,
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0, // ENGBASE_MDP_TDSHP3,
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0, // ENGBASE_MDP_TCC0,
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0, // ENGBASE_MDP_TCC1,
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0, // ENGBASE_MDP_TCC2,
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0, // ENGBASE_MDP_TCC3,
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0, // ENGBASE_MDP_COLOR0,
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0, // ENGBASE_MDP_COLOR1,
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0, // ENGBASE_MMSYS_MUTEX,
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0, // ENGBASE_ISP_MSFDL,
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0, // ENGBASE_ISP_MSS,
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0, // ENGBASE_ISP_MFB,
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0, // ENGBASE_ISP_DIP_A0,
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0, // ENGBASE_ISP_DIP_A1,
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0, // ENGBASE_ISP_DIP_A7,
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0, // ENGBASE_IMGSYS2_CONFIG,
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0, // ENGBASE_ISP_DIP_B0,
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0, // ENGBASE_ISP_DIP_B1,
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0, // ENGBASE_ISP_DIP_B7,
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0, // ENGBASE_ISP_WPE_A,
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0, // ENGBASE_ISP_WPE_B,
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};
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static u32 mdp_base[ENGBASE_COUNT] = {
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[ENGBASE_MMSYS_CONFIG] = 0x1f000000,
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[ENGBASE_MDP_RDMA0] = 0x1f006000,
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[ENGBASE_MDP_RDMA1] = 0x1f007000,
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[ENGBASE_MDP_RDMA2] = 0x1f008000,
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[ENGBASE_MDP_RDMA3] = 0x1f009000,
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[ENGBASE_MDP_FG0] = 0x1f00a000,
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[ENGBASE_MDP_FG1] = 0x1f00b000,
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[ENGBASE_MDP_AAL0] = 0x1f00c000,
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[ENGBASE_MDP_AAL1] = 0x1f00d000,
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[ENGBASE_MDP_AAL2] = 0x1f00e000,
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[ENGBASE_MDP_AAL3] = 0x1f00f000,
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[ENGBASE_MDP_HDR0] = 0x1f010000,
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[ENGBASE_MDP_HDR1] = 0x1f011000,
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[ENGBASE_MDP_RSZ0] = 0x1f012000,
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[ENGBASE_MDP_RSZ1] = 0x1f013000,
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[ENGBASE_MDP_RSZ2] = 0x1f014000,
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[ENGBASE_MDP_RSZ3] = 0x1f015000,
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[ENGBASE_MDP_WROT0] = 0x1f016000,
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[ENGBASE_MDP_WROT1] = 0x1f017000,
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[ENGBASE_MDP_WROT2] = 0x1f018000,
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[ENGBASE_MDP_WROT3] = 0x1f019000,
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[ENGBASE_MDP_TDSHP0] = 0x1f01a000,
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[ENGBASE_MDP_TDSHP1] = 0x1f01b000,
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[ENGBASE_MDP_TDSHP2] = 0x1f01c000,
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[ENGBASE_MDP_TDSHP3] = 0x1f01d000,
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[ENGBASE_MDP_TCC0] = 0x1f01e000,
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[ENGBASE_MDP_TCC1] = 0x1f01f000,
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[ENGBASE_MDP_TCC2] = 0x1f020000,
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[ENGBASE_MDP_TCC3] = 0x1f021000,
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[ENGBASE_MDP_COLOR0] = 0x1f02c000,
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[ENGBASE_MDP_COLOR1] = 0x1f02d000,
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[ENGBASE_MMSYS_MUTEX] = 0x1f001000,
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[ENGBASE_ISP_MSFDL] = 0x15010000,
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[ENGBASE_ISP_MSS] = 0x15012000,
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[ENGBASE_ISP_MFB] = 0x15020000,
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[ENGBASE_ISP_DIP_A0] = 0x15021000,
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[ENGBASE_ISP_DIP_A1] = 0x15022000,
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[ENGBASE_ISP_DIP_A7] = 0x15028000,
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[ENGBASE_IMGSYS2_CONFIG] = 0x15820000,
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[ENGBASE_ISP_DIP_B0] = 0x15821000,
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[ENGBASE_ISP_DIP_B1] = 0x15822000,
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[ENGBASE_ISP_DIP_B7] = 0x15828000,
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[ENGBASE_ISP_WPE_A] = 0x15011000,
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[ENGBASE_ISP_WPE_B] = 0x15811000,
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};
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#endif
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