154 lines
5.2 KiB
ArmAsm
154 lines
5.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/alpha/lib/ev6-csum_ipv6_magic.S
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* 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
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*
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* unsigned short csum_ipv6_magic(struct in6_addr *saddr,
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* struct in6_addr *daddr,
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* __u32 len,
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* unsigned short proto,
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* unsigned int csum);
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*
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* Much of the information about 21264 scheduling/coding comes from:
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* Compiler Writer's Guide for the Alpha 21264
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* abbreviated as 'CWG' in other comments here
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* ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
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* Scheduling notation:
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* E - either cluster
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* U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
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* L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
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* Try not to change the actual algorithm if possible for consistency.
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* Determining actual stalls (other than slotting) doesn't appear to be easy to do.
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*
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* unsigned short csum_ipv6_magic(struct in6_addr *saddr,
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* struct in6_addr *daddr,
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* __u32 len,
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* unsigned short proto,
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* unsigned int csum);
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*
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* Swap <proto> (takes form 0xaabb)
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* Then shift it left by 48, so result is:
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* 0xbbaa0000 00000000
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* Then turn it back into a sign extended 32-bit item
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* 0xbbaa0000
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*
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* Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
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* (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
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* Assume input takes form 0xAABBCCDD
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*
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* Finally, original 'folding' approach is to split the long into 4 unsigned shorts
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* add 4 ushorts, resulting in ushort/carry
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* add carry bits + ushort --> ushort
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* add carry bits + ushort --> ushort (in case the carry results in an overflow)
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* Truncate to a ushort. (took 13 instructions)
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* From doing some testing, using the approach in checksum.c:from64to16()
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* results in the same outcome:
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* split into 2 uints, add those, generating a ulong
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* add the 3 low ushorts together, generating a uint
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* a final add of the 2 lower ushorts
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* truncating the result.
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*
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* Misalignment handling added by Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* The cost is 16 instructions (~8 cycles), including two extra loads which
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* may cause additional delay in rare cases (load-load replay traps).
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*/
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#include <asm/export.h>
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.globl csum_ipv6_magic
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.align 4
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.ent csum_ipv6_magic
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.frame $30,0,$26,0
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csum_ipv6_magic:
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.prologue 0
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ldq_u $0,0($16) # L : Latency: 3
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inslh $18,7,$4 # U : 0000000000AABBCC
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ldq_u $1,8($16) # L : Latency: 3
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sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00
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and $16,7,$6 # E : src misalignment
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ldq_u $5,15($16) # L : Latency: 3
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zapnot $20,15,$20 # U : zero extend incoming csum
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ldq_u $2,0($17) # L : U L U L : Latency: 3
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extql $0,$6,$0 # U :
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extqh $1,$6,$22 # U :
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ldq_u $3,8($17) # L : Latency: 3
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sll $19,24,$19 # U : U U L U : 0x000000aa bb000000
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cmoveq $6,$31,$22 # E : src aligned?
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ldq_u $23,15($17) # L : Latency: 3
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inswl $18,3,$18 # U : 000000CCDD000000
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addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00
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or $0,$22,$0 # E : 1st src word complete
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extql $1,$6,$1 # U :
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or $18,$4,$18 # E : 000000CCDDAABBCC
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extqh $5,$6,$5 # U : L U L U
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and $17,7,$6 # E : dst misalignment
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extql $2,$6,$2 # U :
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or $1,$5,$1 # E : 2nd src word complete
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extqh $3,$6,$22 # U : L U L U :
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cmoveq $6,$31,$22 # E : dst aligned?
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extql $3,$6,$3 # U :
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addq $20,$0,$20 # E : begin summing the words
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extqh $23,$6,$23 # U : L U L U :
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srl $18,16,$4 # U : 0000000000CCDDAA
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or $2,$22,$2 # E : 1st dst word complete
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zap $19,0x3,$19 # U : <sign bits>bbaa0000
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or $3,$23,$3 # E : U L U L : 2nd dst word complete
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cmpult $20,$0,$0 # E :
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addq $20,$1,$20 # E :
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zapnot $18,0xa,$18 # U : 00000000DD00BB00
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zap $4,0xa,$4 # U : U U L L : 0000000000CC00AA
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or $18,$4,$18 # E : 00000000DDCCBBAA
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nop # E :
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cmpult $20,$1,$1 # E :
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addq $20,$2,$20 # E : U L U L
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cmpult $20,$2,$2 # E :
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addq $20,$3,$20 # E :
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cmpult $20,$3,$3 # E : (1 cycle stall on $20)
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addq $20,$18,$20 # E : U L U L (1 cycle stall on $20)
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cmpult $20,$18,$18 # E :
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addq $20,$19,$20 # E : (1 cycle stall on $20)
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addq $0,$1,$0 # E : merge the carries back into the csum
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addq $2,$3,$2 # E :
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cmpult $20,$19,$19 # E :
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addq $18,$19,$18 # E : (1 cycle stall on $19)
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addq $0,$2,$0 # E :
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addq $20,$18,$20 # E : U L U L :
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/* (1 cycle stall on $18, 2 cycles on $20) */
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addq $0,$20,$0 # E :
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zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0)
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nop # E :
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srl $0,32,$0 # U : U L U L : (1 cycle stall on $0)
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addq $1,$0,$1 # E : Finished generating ulong
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extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1)
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zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1)
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extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1)
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addq $0,$2,$0 # E
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addq $0,$1,$3 # E : Finished generating uint
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/* (1 cycle stall on $0) */
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extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3)
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nop # E : L U L U
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addq $1,$3,$0 # E : Final carry
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not $0,$4 # E : complement (1 cycle stall on $0)
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zapnot $4,3,$0 # U : clear upper garbage bits
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/* (1 cycle stall on $4) */
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ret # L0 : L U L U
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.end csum_ipv6_magic
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EXPORT_SYMBOL(csum_ipv6_magic)
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