575 lines
15 KiB
Plaintext
575 lines
15 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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&main_pmic {
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compatible = "mediatek,mt6358-pmic";
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interrupt-controller;
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#interrupt-cells = <2>;
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mediatek,num-pmic-irqs = <145>;
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mediatek,pmic-irqs =
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<INT_VPROC11_OC SP_BUCK>,
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<INT_VPROC12_OC SP_BUCK>,
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<INT_VCORE_OC SP_BUCK>,
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<INT_VGPU_OC SP_BUCK>,
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<INT_VMODEM_OC SP_BUCK>,
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<INT_VDRAM1_OC SP_BUCK>,
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<INT_VS1_OC SP_BUCK>,
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<INT_VS2_OC SP_BUCK>,
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<INT_VPA_OC SP_BUCK>,
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<INT_VCORE_PREOC SP_BUCK>,
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<INT_VFE28_OC SP_LDO>,
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<INT_VXO22_OC SP_LDO>,
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<INT_VRF18_OC SP_LDO>,
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<INT_VRF12_OC SP_LDO>,
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<INT_VEFUSE_OC SP_LDO>,
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<INT_VCN33_OC SP_LDO>,
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<INT_VCN28_OC SP_LDO>,
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<INT_VCN18_OC SP_LDO>,
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<INT_VM18_OC SP_LDO>,
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<INT_VMDDR_OC SP_LDO>,
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<INT_VSRAM_CORE_OC SP_LDO>,
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<INT_VA12_OC SP_LDO>,
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<INT_VAUX18_OC SP_LDO>,
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<INT_VAUD28_OC SP_LDO>,
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<INT_VIO28_OC SP_LDO>,
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<INT_VIO18_OC SP_LDO>,
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<INT_VSRAM_PROC11_OC SP_LDO>,
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<INT_VSRAM_PROC12_OC SP_LDO>,
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<INT_VSRAM_OTHERS_OC SP_LDO>,
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<INT_VSRAM_GPU_OC SP_LDO>,
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<INT_VDRAM2_OC SP_LDO>,
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<INT_VMC_OC SP_LDO>,
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<INT_VMCH_OC SP_LDO>,
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<INT_VEMC_OC SP_LDO>,
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<INT_VSIM1_OC SP_LDO>,
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<INT_VSIM2_OC SP_LDO>,
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<INT_VIBR_OC SP_LDO>,
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<INT_VUSB_OC SP_LDO>,
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<INT_VBIF28_OC SP_LDO>,
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<INT_PWRKEY SP_PSC>,
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<INT_HOMEKEY SP_PSC>,
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<INT_PWRKEY_R SP_PSC>,
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<INT_HOMEKEY_R SP_PSC>,
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<INT_NI_LBAT_INT SP_PSC>,
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<INT_CHRDET SP_PSC>,
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<INT_CHRDET_EDGE SP_PSC>,
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<INT_VCDT_HV_DET SP_PSC>,
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<INT_RTC SP_SCK>,
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<INT_FG_BAT0_H SP_BM>,
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<INT_FG_BAT0_L SP_BM>,
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<INT_FG_CUR_H SP_BM>,
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<INT_FG_CUR_L SP_BM>,
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<INT_FG_ZCV SP_BM>,
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<INT_FG_BAT1_H SP_BM>,
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<INT_FG_BAT1_L SP_BM>,
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<INT_FG_N_CHARGE_L SP_BM>,
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<INT_FG_IAVG_H SP_BM>,
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<INT_FG_IAVG_L SP_BM>,
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<INT_FG_TIME_H SP_BM>,
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<INT_FG_DISCHARGE SP_BM>,
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<INT_FG_CHARGE SP_BM>,
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<INT_BATON_LV SP_BM>,
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<INT_BATON_HT SP_BM>,
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<INT_BATON_BAT_IN SP_BM>,
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<INT_BATON_BAT_OUT SP_BM>,
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<INT_BIF SP_BM>,
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<INT_BAT_H SP_HK>,
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<INT_BAT_L SP_HK>,
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<INT_BAT2_H SP_HK>,
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<INT_BAT2_L SP_HK>,
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<INT_BAT_TEMP_H SP_HK>,
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<INT_BAT_TEMP_L SP_HK>,
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<INT_AUXADC_IMP SP_HK>,
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<INT_NAG_C_DLTV SP_HK>,
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<INT_AUDIO SP_AUD>,
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<INT_ACCDET SP_AUD>,
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<INT_ACCDET_EINT0 SP_AUD>,
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<INT_ACCDET_EINT1 SP_AUD>,
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<INT_SPI_CMD_ALERT SP_MISC>;
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interrupt-names =
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"vproc11_oc",
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"vproc12_oc",
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"vcore_oc",
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"vgpu_oc",
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"vmodem_oc",
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"vdram1_oc",
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"vs1_oc",
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"vs2_oc",
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"vpa_oc",
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"vcore_preoc",
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"vfe28_oc",
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"vxo22_oc",
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"vrf18_oc",
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"vrf12_oc",
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"vefuse_oc",
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"vcn33_oc",
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"vcn28_oc",
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"vcn18_oc",
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"vm18_oc",
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"vmddr_oc",
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"vsram_core_oc",
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"va12_oc",
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"vaux18_oc",
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"vaud28_oc",
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"vio28_oc",
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"vio18_oc",
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"vsram_proc11_oc",
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"vsram_proc12_oc",
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"vsram_others_oc",
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"vsram_gpu_oc",
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"vdram2_oc",
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"vmc_oc",
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"vmch_oc",
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"vemc_oc",
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"vsim1_oc",
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"vsim2_oc",
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"vibr_oc",
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"vusb_oc",
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"vbif28_oc",
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"pwrkey",
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"homekey",
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"pwrkey_r",
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"homekey_r",
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"ni_lbat_int",
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"chrdet",
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"chrdet_edge",
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"vcdt_hv_det",
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"rtc",
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"fg_bat0_h",
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"fg_bat0_l",
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"fg_cur_h",
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"fg_cur_l",
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"fg_zcv",
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"fg_bat1_h",
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"fg_bat1_l",
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"fg_n_charge_l",
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"fg_iavg_h",
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"fg_iavg_l",
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"fg_time_h",
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"fg_discharge",
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"fg_charge",
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"baton_lv",
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"baton_ht",
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"baton_bat_in",
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"baton_bat_out",
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"bif",
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"bat_h",
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"bat_l",
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"bat2_h",
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"bat2_l",
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"bat_temp_h",
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"bat_temp_l",
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"auxadc_imp",
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"nag_c_dltv",
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"audio",
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"accdet",
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"accdet_eint0",
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"accdet_eint1",
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"spi_cmd_alert";
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pmic: mt-pmic {
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compatible = "mediatek,mt-pmic";
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interrupts = <INT_PWRKEY IRQ_TYPE_LEVEL_HIGH>,
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<INT_PWRKEY_R IRQ_TYPE_LEVEL_HIGH>,
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<INT_HOMEKEY IRQ_TYPE_LEVEL_HIGH>,
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<INT_HOMEKEY_R IRQ_TYPE_LEVEL_HIGH>,
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<INT_BAT_H IRQ_TYPE_LEVEL_HIGH>,
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<INT_BAT_L IRQ_TYPE_LEVEL_HIGH>,
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<INT_FG_CUR_H IRQ_TYPE_LEVEL_HIGH>,
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<INT_FG_CUR_L IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwrkey",
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"pwrkey_r",
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"homekey",
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"homekey_r",
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"bat_h",
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"bat_l",
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"fg_cur_h",
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"fg_cur_l";
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/* WK for power plan change */
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pmic,init_gpio = <&pio 200 0x0>;
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};
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pmic_auxadc: mt635x-auxadc {
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compatible = "mediatek,mt6358-auxadc";
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#io-channel-cells = <1>;
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/* efuse offset from mt6358 */
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cali-efuse-offset = <1>;
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batadc {
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channel = <AUXADC_BATADC>;
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resistance-ratio = <3 1>;
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avg-num = <128>;
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};
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vcdt {
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channel = <AUXADC_VCDT>;
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};
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bat_temp {
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channel = <AUXADC_BAT_TEMP>;
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resistance-ratio = <2 1>;
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};
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chip_temp {
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channel = <AUXADC_CHIP_TEMP>;
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};
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vcore_temp {
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channel = <AUXADC_VCORE_TEMP>;
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};
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vproc_temp {
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channel = <AUXADC_VPROC_TEMP>;
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};
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vgpu_temp {
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channel = <AUXADC_VGPU_TEMP>;
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};
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accdet {
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channel = <AUXADC_ACCDET>;
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};
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dcxo_volt {
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channel = <AUXADC_VDCXO>;
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resistance-ratio = <3 2>;
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};
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tsx_temp {
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channel = <AUXADC_TSX_TEMP>;
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avg-num = <128>;
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};
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hpofs_cal {
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channel = <AUXADC_HPOFS_CAL>;
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avg-num = <256>;
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};
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dcxo_temp {
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channel = <AUXADC_DCXO_TEMP>;
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avg-num = <16>;
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};
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vbif {
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channel = <AUXADC_VBIF>;
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resistance-ratio = <2 1>;
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};
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};
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mt6358regulator: mt6358regulator {
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compatible = "mediatek,mt6358-regulator";
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interrupts =
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<INT_VPROC11_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VPROC12_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VCORE_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VGPU_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VMODEM_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VDRAM1_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VS1_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VS2_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VPA_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VFE28_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VXO22_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VRF18_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VRF12_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VEFUSE_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VCN33_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VCN28_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VCN18_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VM18_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VMDDR_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSRAM_CORE_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VA12_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VAUX18_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VAUD28_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VIO28_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VIO18_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSRAM_PROC11_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSRAM_PROC12_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSRAM_OTHERS_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSRAM_GPU_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VDRAM2_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VMC_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VMCH_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VEMC_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSIM1_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VSIM2_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VIBR_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VUSB_OC IRQ_TYPE_LEVEL_HIGH>,
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<INT_VBIF28_OC IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names =
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"VPROC11",
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"VPROC12",
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"VCORE",
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"VGPU",
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"VMODEM",
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"VDRAM1",
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"VS1",
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"VS2",
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"VPA",
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"VFE28",
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"VXO22",
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"VRF18",
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"VRF12",
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"VEFUSE",
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"VCN33_BT",
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"VCN28",
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"VCN18",
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"VM18",
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"VMDDR",
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"VSRAM_CORE",
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"VA12",
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"VAUX18",
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"VAUD28",
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"VIO28",
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"VIO18",
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"VSRAM_PROC11",
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"VSRAM_PROC12",
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"VSRAM_OTHERS",
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"VSRAM_GPU",
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"VDRAM2",
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"VMC",
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"VMCH",
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"VEMC",
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"VSIM1",
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"VSIM2",
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"VIBR",
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"VUSB",
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"VBIF28";
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mt_pmic_vdram1_buck_reg: buck_vdram1 {
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regulator-name = "vdram1";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <2087500>;
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regulator-enable-ramp-delay = <0>;
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};
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mt_pmic_vcore_buck_reg: buck_vcore {
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regulator-name = "vcore";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <200>;
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};
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mt_pmic_vpa_buck_reg: buck_vpa {
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regulator-name = "vpa";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3650000>;
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regulator-enable-ramp-delay = <250>;
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};
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mt_pmic_vproc11_buck_reg: buck_vproc11 {
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regulator-name = "vproc11";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <200>;
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};
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mt_pmic_vproc12_buck_reg: buck_vproc12 {
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regulator-name = "vproc12";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <200>;
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};
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mt_pmic_vgpu_buck_reg: buck_vgpu {
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regulator-name = "vgpu";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <200>;
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};
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mt_pmic_vs2_buck_reg: buck_vs2 {
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regulator-name = "vs2";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <2087500>;
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regulator-enable-ramp-delay = <0>;
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};
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mt_pmic_vmodem_buck_reg: buck_vmodem {
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regulator-name = "vmodem";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <900>;
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};
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mt_pmic_vs1_buck_reg: buck_vs1 {
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regulator-name = "vs1";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <2587500>;
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regulator-enable-ramp-delay = <0>;
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};
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mt_pmic_vdram2_ldo_reg: ldo_vdram2 {
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regulator-name = "vdram2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <3300>;
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};
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mt_pmic_vsim1_ldo_reg: ldo_vsim1 {
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regulator-name = "vsim1";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <540>;
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};
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mt_pmic_vibr_ldo_reg: ldo_vibr {
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regulator-name = "vibr";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <60>;
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};
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mt_pmic_vrf12_ldo_reg: ldo_vrf12 {
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regulator-name = "vrf12";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <120>;
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};
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mt_pmic_vio18_ldo_reg: ldo_vio18 {
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regulator-name = "vio18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <2700>;
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regulator-always-on;
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};
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mt_pmic_vusb_ldo_reg: ldo_vusb {
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regulator-name = "vusb";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <270>;
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};
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mt_pmic_vcn18_ldo_reg: ldo_vcn18 {
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regulator-name = "vcn18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <270>;
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};
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mt_pmic_vfe28_ldo_reg: ldo_vfe28 {
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regulator-name = "vfe28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <270>;
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};
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mt_pmic_vsram_proc11_ldo_reg: ldo_vsram_proc11 {
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regulator-name = "vsram_proc11";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <240>;
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};
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mt_pmic_vcn28_ldo_reg: ldo_vcn28 {
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regulator-name = "vcn28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <270>;
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};
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mt_pmic_vsram_core_ldo_reg: ldo_vsram_core {
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regulator-name = "vsram_core";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
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regulator-enable-ramp-delay = <240>;
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};
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mt_pmic_vsram_others_ldo_reg: ldo_vsram_others {
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regulator-name = "vsram_others";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1293750>;
|
|
regulator-enable-ramp-delay = <240>;
|
|
};
|
|
mt_pmic_vsram_gpu_ldo_reg: ldo_vsram_gpu {
|
|
regulator-name = "vsram_gpu";
|
|
regulator-min-microvolt = <500000>;
|
|
regulator-max-microvolt = <1293750>;
|
|
regulator-enable-ramp-delay = <240>;
|
|
};
|
|
mt_pmic_vxo22_ldo_reg: ldo_vxo22 {
|
|
regulator-name = "vxo22";
|
|
regulator-min-microvolt = <2200000>;
|
|
regulator-max-microvolt = <2200000>;
|
|
regulator-enable-ramp-delay = <120>;
|
|
};
|
|
mt_pmic_vefuse_ldo_reg: ldo_vefuse {
|
|
regulator-name = "vefuse";
|
|
regulator-min-microvolt = <1700000>;
|
|
regulator-max-microvolt = <1900000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vaux18_ldo_reg: ldo_vaux18 {
|
|
regulator-name = "vaux18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vmch_ldo_reg: ldo_vmch {
|
|
regulator-name = "vmch";
|
|
regulator-min-microvolt = <2900000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <60>;
|
|
};
|
|
mt_pmic_vbif28_ldo_reg: ldo_vbif28 {
|
|
regulator-name = "vbif28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vsram_proc12_ldo_reg: ldo_vsram_proc12 {
|
|
regulator-name = "vsram_proc12";
|
|
regulator-min-microvolt = <500000>;
|
|
regulator-max-microvolt = <1293750>;
|
|
regulator-enable-ramp-delay = <240>;
|
|
};
|
|
mt_pmic_vemc_ldo_reg: ldo_vemc {
|
|
regulator-name = "vemc";
|
|
regulator-min-microvolt = <2900000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <60>;
|
|
};
|
|
mt_pmic_vio28_ldo_reg: ldo_vio28 {
|
|
regulator-name = "vio28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_va12_ldo_reg: ldo_va12 {
|
|
regulator-name = "va12";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
regulator-always-on;
|
|
};
|
|
mt_pmic_vrf18_ldo_reg: ldo_vrf18 {
|
|
regulator-name = "vrf18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <120>;
|
|
};
|
|
mt_pmic_vcn33_bt_ldo_reg: ldo_vcn33_bt {
|
|
regulator-name = "vcn33_bt";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3500000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vcn33_wifi_ldo_reg: ldo_vcn33_wifi {
|
|
regulator-name = "vcn33_wifi";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3500000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vmc_ldo_reg: ldo_vmc {
|
|
regulator-name = "vmc";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <60>;
|
|
};
|
|
mt_pmic_vaud28_ldo_reg: ldo_vaud28 {
|
|
regulator-name = "vaud28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <270>;
|
|
};
|
|
mt_pmic_vsim2_ldo_reg: ldo_vsim2 {
|
|
regulator-name = "vsim2";
|
|
regulator-min-microvolt = <1700000>;
|
|
regulator-max-microvolt = <3100000>;
|
|
regulator-enable-ramp-delay = <540>;
|
|
};
|
|
mt_pmic_va09_ldo_reg: ldo_va09 {
|
|
regulator-name = "va09";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <900000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
regulator-boot-on;
|
|
};
|
|
}; /* End of mt6358regulator */
|
|
mt6358_rtc: mt6358_rtc {
|
|
compatible = "mediatek,mt6358-rtc";
|
|
bootmode = <&chosen>;
|
|
interrupts = <INT_RTC IRQ_TYPE_NONE>;
|
|
interrupt-names = "rtc";
|
|
base = <0x580>;
|
|
};
|
|
mt6358_misc: mt6358_misc {
|
|
compatible = "mediatek,mt6358-misc";
|
|
base = <0x580>;
|
|
dcxo-switch;
|
|
};
|
|
};/* End of main_pmic */
|