724 lines
21 KiB
C
724 lines
21 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X common routines
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/ath79-clk.h>
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#include <asm/div64.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "machtypes.h"
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#define AR71XX_BASE_FREQ 40000000
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#define AR724X_BASE_FREQ 40000000
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static struct clk *clks[ATH79_CLK_END];
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static struct clk_onecell_data clk_data = {
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.clks = clks,
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.clk_num = ARRAY_SIZE(clks),
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};
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static struct clk *__init ath79_add_sys_clkdev(
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const char *id, unsigned long rate)
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{
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struct clk *clk;
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int err;
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clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
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if (IS_ERR(clk))
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panic("failed to allocate %s clock structure", id);
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err = clk_register_clkdev(clk, id, NULL);
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if (err)
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panic("unable to register %s clock device", id);
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return clk;
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}
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static void __init ar71xx_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ref_rate = AR71XX_BASE_FREQ;
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pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
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freq = div * ref_rate;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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cpu_rate = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ddr_rate = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static struct clk * __init ath79_reg_ffclk(const char *name,
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const char *parent_name, unsigned int mult, unsigned int div)
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{
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struct clk *clk;
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clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
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if (IS_ERR(clk))
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panic("failed to allocate %s clock structure", name);
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return clk;
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}
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static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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{
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u32 pll;
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u32 mult, div, ddr_div, ahb_div;
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pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
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mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
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ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
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clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
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clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
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}
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static void __init ar724x_clocks_init(void)
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{
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struct clk *ref_clk;
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ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
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ar724x_clk_init(ref_clk, ath79_pll_base);
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/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
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clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
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clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
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clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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{
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u32 clock_ctrl;
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u32 ref_div;
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u32 ninit_mul;
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u32 out_div;
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u32 cpu_div;
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u32 ddr_div;
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u32 ahb_div;
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clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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ref_div = 1;
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ninit_mul = 1;
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out_div = 1;
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cpu_div = 1;
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ddr_div = 1;
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ahb_div = 1;
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} else {
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u32 cpu_config;
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u32 t;
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cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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ref_div = t;
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ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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out_div = (1 << t);
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cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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}
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clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
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ninit_mul, ref_div * out_div * cpu_div);
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clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
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ninit_mul, ref_div * out_div * ddr_div);
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clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
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ninit_mul, ref_div * out_div * ahb_div);
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}
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static void __init ar933x_clocks_init(void)
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{
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struct clk *ref_clk;
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unsigned long ref_rate;
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u32 t;
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t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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ref_rate = (40 * 1000 * 1000);
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else
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ref_rate = (25 * 1000 * 1000);
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ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
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ar9330_clk_init(ref_clk, ath79_pll_base);
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/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
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clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
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clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
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clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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u32 frac, u32 out_div)
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{
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u64 t;
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u32 ret;
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t = ref;
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t *= nint;
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do_div(t, ref_div);
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ret = t;
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t = ref;
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t *= nfrac;
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do_div(t, ref_div * frac);
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ret += t;
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ret /= (1 << out_div);
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return ret;
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}
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static void __init ar934x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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void __iomem *dpll_base;
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dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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AR934X_SRIF_DPLL2_OUTDIV_MASK;
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
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nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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AR934X_SRIF_DPLL1_NINT_MASK;
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nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NINT_MASK;
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nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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frac = 1 << 6;
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}
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cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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AR934X_SRIF_DPLL2_OUTDIV_MASK;
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pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
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nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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AR934X_SRIF_DPLL1_NINT_MASK;
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nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NINT_MASK;
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nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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frac = 1 << 10;
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}
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ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = cpu_pll / (postdiv + 1);
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else
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cpu_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddr_rate = ddr_pll / (postdiv + 1);
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else
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ddr_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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iounmap(dpll_base);
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}
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static void __init qca953x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += frac * (ref_rate >> 6) / ref_div;
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = cpu_pll / (postdiv + 1);
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else
|
|
cpu_rate = ddr_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
|
QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
|
ddr_rate = ref_rate;
|
|
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
|
ddr_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
ddr_rate = cpu_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
|
QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
|
ahb_rate = ref_rate;
|
|
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
|
ahb_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
ahb_rate = cpu_pll / (postdiv + 1);
|
|
|
|
ath79_add_sys_clkdev("ref", ref_rate);
|
|
ath79_add_sys_clkdev("cpu", cpu_rate);
|
|
ath79_add_sys_clkdev("ddr", ddr_rate);
|
|
ath79_add_sys_clkdev("ahb", ahb_rate);
|
|
|
|
clk_add_alias("wdt", NULL, "ref", NULL);
|
|
clk_add_alias("uart", NULL, "ref", NULL);
|
|
}
|
|
|
|
static void __init qca955x_clocks_init(void)
|
|
{
|
|
unsigned long ref_rate;
|
|
unsigned long cpu_rate;
|
|
unsigned long ddr_rate;
|
|
unsigned long ahb_rate;
|
|
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
|
u32 cpu_pll, ddr_pll;
|
|
u32 bootstrap;
|
|
|
|
bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
|
|
if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
|
|
ref_rate = 40 * 1000 * 1000;
|
|
else
|
|
ref_rate = 25 * 1000 * 1000;
|
|
|
|
pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
|
|
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
|
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
|
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
|
QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
|
|
nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
|
QCA955X_PLL_CPU_CONFIG_NINT_MASK;
|
|
frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
|
QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
|
|
|
|
cpu_pll = nint * ref_rate / ref_div;
|
|
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
|
|
cpu_pll /= (1 << out_div);
|
|
|
|
pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
|
|
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
|
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
|
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
|
QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
|
|
nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
|
QCA955X_PLL_DDR_CONFIG_NINT_MASK;
|
|
frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
|
QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
|
|
|
|
ddr_pll = nint * ref_rate / ref_div;
|
|
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
|
|
ddr_pll /= (1 << out_div);
|
|
|
|
clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
|
|
|
|
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
|
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
|
cpu_rate = ref_rate;
|
|
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
|
cpu_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
cpu_rate = cpu_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
|
QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
|
ddr_rate = ref_rate;
|
|
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
|
ddr_rate = cpu_pll / (postdiv + 1);
|
|
else
|
|
ddr_rate = ddr_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
|
QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
|
ahb_rate = ref_rate;
|
|
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
|
ahb_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
ahb_rate = cpu_pll / (postdiv + 1);
|
|
|
|
ath79_add_sys_clkdev("ref", ref_rate);
|
|
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
|
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
|
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
|
|
|
clk_add_alias("wdt", NULL, "ref", NULL);
|
|
clk_add_alias("uart", NULL, "ref", NULL);
|
|
}
|
|
|
|
static void __init qca956x_clocks_init(void)
|
|
{
|
|
unsigned long ref_rate;
|
|
unsigned long cpu_rate;
|
|
unsigned long ddr_rate;
|
|
unsigned long ahb_rate;
|
|
u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
|
|
u32 cpu_pll, ddr_pll;
|
|
u32 bootstrap;
|
|
|
|
/*
|
|
* QCA956x timer init workaround has to be applied right before setting
|
|
* up the clock. Else, there will be no jiffies
|
|
*/
|
|
u32 misc;
|
|
|
|
misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
|
|
misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
|
|
ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
|
|
|
|
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
|
|
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
|
|
ref_rate = 40 * 1000 * 1000;
|
|
else
|
|
ref_rate = 25 * 1000 * 1000;
|
|
|
|
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
|
|
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
|
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
|
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
|
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
|
|
|
|
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
|
|
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
|
|
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
|
|
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
|
|
QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
|
|
lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
|
|
QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
|
|
|
|
cpu_pll = nint * ref_rate / ref_div;
|
|
cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
|
|
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
|
|
cpu_pll /= (1 << out_div);
|
|
|
|
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
|
|
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
|
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
|
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
|
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
|
|
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
|
|
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
|
|
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
|
|
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
|
|
QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
|
|
lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
|
|
QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
|
|
|
|
ddr_pll = nint * ref_rate / ref_div;
|
|
ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
|
|
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
|
|
ddr_pll /= (1 << out_div);
|
|
|
|
clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
|
|
|
|
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
|
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
|
cpu_rate = ref_rate;
|
|
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
|
|
cpu_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
cpu_rate = cpu_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
|
QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
|
ddr_rate = ref_rate;
|
|
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
|
|
ddr_rate = cpu_pll / (postdiv + 1);
|
|
else
|
|
ddr_rate = ddr_pll / (postdiv + 1);
|
|
|
|
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
|
QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
|
|
|
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
|
ahb_rate = ref_rate;
|
|
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
|
ahb_rate = ddr_pll / (postdiv + 1);
|
|
else
|
|
ahb_rate = cpu_pll / (postdiv + 1);
|
|
|
|
ath79_add_sys_clkdev("ref", ref_rate);
|
|
ath79_add_sys_clkdev("cpu", cpu_rate);
|
|
ath79_add_sys_clkdev("ddr", ddr_rate);
|
|
ath79_add_sys_clkdev("ahb", ahb_rate);
|
|
|
|
clk_add_alias("wdt", NULL, "ref", NULL);
|
|
clk_add_alias("uart", NULL, "ref", NULL);
|
|
}
|
|
|
|
void __init ath79_clocks_init(void)
|
|
{
|
|
if (soc_is_ar71xx())
|
|
ar71xx_clocks_init();
|
|
else if (soc_is_ar724x() || soc_is_ar913x())
|
|
ar724x_clocks_init();
|
|
else if (soc_is_ar933x())
|
|
ar933x_clocks_init();
|
|
else if (soc_is_ar934x())
|
|
ar934x_clocks_init();
|
|
else if (soc_is_qca953x())
|
|
qca953x_clocks_init();
|
|
else if (soc_is_qca955x())
|
|
qca955x_clocks_init();
|
|
else if (soc_is_qca956x() || soc_is_tp9343())
|
|
qca956x_clocks_init();
|
|
else
|
|
BUG();
|
|
}
|
|
|
|
unsigned long __init
|
|
ath79_get_sys_clk_rate(const char *id)
|
|
{
|
|
struct clk *clk;
|
|
unsigned long rate;
|
|
|
|
clk = clk_get(NULL, id);
|
|
if (IS_ERR(clk))
|
|
panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
|
|
|
|
rate = clk_get_rate(clk);
|
|
clk_put(clk);
|
|
|
|
return rate;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static void __init ath79_clocks_init_dt(struct device_node *np)
|
|
{
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
|
|
|
|
static void __init ath79_clocks_init_dt_ng(struct device_node *np)
|
|
{
|
|
struct clk *ref_clk;
|
|
void __iomem *pll_base;
|
|
|
|
ref_clk = of_clk_get(np, 0);
|
|
if (IS_ERR(ref_clk)) {
|
|
pr_err("%pOF: of_clk_get failed\n", np);
|
|
goto err;
|
|
}
|
|
|
|
pll_base = of_iomap(np, 0);
|
|
if (!pll_base) {
|
|
pr_err("%pOF: can't map pll registers\n", np);
|
|
goto err_clk;
|
|
}
|
|
|
|
if (of_device_is_compatible(np, "qca,ar9130-pll"))
|
|
ar724x_clk_init(ref_clk, pll_base);
|
|
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
|
|
ar9330_clk_init(ref_clk, pll_base);
|
|
else {
|
|
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
|
|
pr_err("%pOF: could not register clk provider\n", np);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
return;
|
|
|
|
err_iounmap:
|
|
iounmap(pll_base);
|
|
|
|
err_clk:
|
|
clk_put(ref_clk);
|
|
|
|
err:
|
|
return;
|
|
}
|
|
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
|
|
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
|
|
#endif
|