189 lines
3.7 KiB
ArmAsm
189 lines
3.7 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1998 by Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* Further modifications to make this work:
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* Copyright (c) 1998 Harald Koerfgen
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/errno.h>
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#include <asm/export.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#define EX(a,b) \
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9: a,##b; \
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.section __ex_table,"a"; \
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PTR 9b,fault; \
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.previous
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#define EX2(a,b) \
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9: a,##b; \
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.section __ex_table,"a"; \
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PTR 9b,bad_stack; \
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PTR 9b+4,bad_stack; \
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.previous
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.set mips1
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/*
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* Save a thread's fp context.
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*/
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LEAF(_save_fp)
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EXPORT_SYMBOL(_save_fp)
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fpu_save_single a0, t1 # clobbers t1
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jr ra
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END(_save_fp)
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/*
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* Restore a thread's fp context.
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*/
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LEAF(_restore_fp)
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fpu_restore_single a0, t1 # clobbers t1
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jr ra
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END(_restore_fp)
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* The value to initialize fcr31 to comes in $a0.
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*/
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.set push
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SET_HARDFLOAT
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LEAF(_init_fpu)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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ctc1 a0, fcr31
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li t0, -1
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mtc1 t0, $f0
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mtc1 t0, $f1
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mtc1 t0, $f2
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mtc1 t0, $f3
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mtc1 t0, $f4
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mtc1 t0, $f5
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mtc1 t0, $f6
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mtc1 t0, $f7
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mtc1 t0, $f8
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mtc1 t0, $f9
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mtc1 t0, $f10
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mtc1 t0, $f11
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mtc1 t0, $f12
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mtc1 t0, $f13
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mtc1 t0, $f14
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mtc1 t0, $f15
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mtc1 t0, $f16
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mtc1 t0, $f17
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mtc1 t0, $f18
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mtc1 t0, $f19
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mtc1 t0, $f20
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mtc1 t0, $f21
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mtc1 t0, $f22
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mtc1 t0, $f23
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mtc1 t0, $f24
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mtc1 t0, $f25
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mtc1 t0, $f26
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mtc1 t0, $f27
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mtc1 t0, $f28
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mtc1 t0, $f29
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mtc1 t0, $f30
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mtc1 t0, $f31
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jr ra
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END(_init_fpu)
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.set pop
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.set noreorder
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/**
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* _save_fp_context() - save FP context from the FPU
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* @a0 - pointer to fpregs field of sigcontext
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* @a1 - pointer to fpc_csr field of sigcontext
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*
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* Save FP context, including the 32 FP data registers and the FP
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* control & status register, from the FPU to signal context.
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*/
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LEAF(_save_fp_context)
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.set push
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SET_HARDFLOAT
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li v0, 0 # assume success
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cfc1 t1, fcr31
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EX2(s.d $f0, 0(a0))
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EX2(s.d $f2, 16(a0))
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EX2(s.d $f4, 32(a0))
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EX2(s.d $f6, 48(a0))
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EX2(s.d $f8, 64(a0))
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EX2(s.d $f10, 80(a0))
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EX2(s.d $f12, 96(a0))
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EX2(s.d $f14, 112(a0))
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EX2(s.d $f16, 128(a0))
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EX2(s.d $f18, 144(a0))
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EX2(s.d $f20, 160(a0))
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EX2(s.d $f22, 176(a0))
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EX2(s.d $f24, 192(a0))
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EX2(s.d $f26, 208(a0))
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EX2(s.d $f28, 224(a0))
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EX2(s.d $f30, 240(a0))
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jr ra
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EX(sw t1, (a1))
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.set pop
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END(_save_fp_context)
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/**
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* _restore_fp_context() - restore FP context to the FPU
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* @a0 - pointer to fpregs field of sigcontext
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* @a1 - pointer to fpc_csr field of sigcontext
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*
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* Restore FP context, including the 32 FP data registers and the FP
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* control & status register, from signal context to the FPU.
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*/
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LEAF(_restore_fp_context)
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.set push
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SET_HARDFLOAT
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li v0, 0 # assume success
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EX(lw t0, (a1))
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EX2(l.d $f0, 0(a0))
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EX2(l.d $f2, 16(a0))
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EX2(l.d $f4, 32(a0))
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EX2(l.d $f6, 48(a0))
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EX2(l.d $f8, 64(a0))
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EX2(l.d $f10, 80(a0))
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EX2(l.d $f12, 96(a0))
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EX2(l.d $f14, 112(a0))
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EX2(l.d $f16, 128(a0))
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EX2(l.d $f18, 144(a0))
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EX2(l.d $f20, 160(a0))
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EX2(l.d $f22, 176(a0))
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EX2(l.d $f24, 192(a0))
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EX2(l.d $f26, 208(a0))
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EX2(l.d $f28, 224(a0))
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EX2(l.d $f30, 240(a0))
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jr ra
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ctc1 t0, fcr31
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.set pop
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END(_restore_fp_context)
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.set reorder
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.type fault, @function
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.ent fault
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fault: li v0, -EFAULT
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jr ra
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.end fault
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