66 lines
1.4 KiB
C
66 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRV_CLK_MT6877_H
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#define __DRV_CLK_MT6877_H
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#define MT_CCF_PLL_DISABLE 0
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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#define MT6877_PLL_FMAX (3800UL * MHZ)
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#define MT6877_PLL_FMIN (1500UL * MHZ)
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#define MT6877_INTEGER_BITS 8
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#define MFGPLL1 "mfg_ao_mfgpll1"
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#define MFGPLL2 "mfg_ao_mfgpll2"
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#define MFGPLL3 "mfg_ao_mfgpll3"
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#define MFGPLL4 "mfg_ao_mfgpll4"
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#if MT_CCF_PLL_DISABLE
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#define PLL_CFLAGS PLL_AO
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#else
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#define PLL_CFLAGS (0)
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#endif
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#define PLL_PWR(_id, _name, _reg, _en_reg, _en_mask, \
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_pwr_reg, _flags, \
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_pd_reg, _pd_shift, \
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_pcw_reg, _pcw_shift, _pcwbits, \
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_pwr_stat) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.en_reg = _en_reg, \
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.en_mask = _en_mask, \
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.pwr_reg = _pwr_reg, \
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.flags = (_flags | PLL_CFLAGS), \
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.fmax = MT6877_PLL_FMAX, \
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.fmin = MT6877_PLL_FMIN, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT6877_INTEGER_BITS, \
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.pwr_stat = _pwr_stat, \
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}
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enum subsys_id {
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APMIXEDSYS = 0,
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GPU_PLL_CTRL = 1,
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PLL_SYS_NUM = 2,
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};
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extern int clk_mt6877_pll_registration(enum subsys_id id,
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const struct mtk_pll_data *plls,
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struct platform_device *pdev,
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int num_plls);
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#endif/* __DRV_CLK_MT6877_H */
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