55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_FREQHOPPING_H__
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#define __MT_FREQHOPPING_H__
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enum FH_PLL_ID {
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FH_TOP_PLL0 = 0, /*ARMPLL_LL */
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FH_TOP_PLL1 = 1, /*ARMPLL_BL0 */
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FH_TOP_PLL2 = 2, /*ARMPLL_B */
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FH_TOP_PLL3 = 3, /*CCIPLL */
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FH_TOP_PLL4 = 4, /*MEMPLL */
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FH_TOP_PLL5 = 5, /*EMIPLL */
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FH_TOP_PLL6 = 6, /*MPLL */
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FH_TOP_PLL7 = 7, /*MMPLL */
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FH_TOP_PLL8 = 8, /*MAINPLL */
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FH_TOP_PLL9 = 9, /*MSDCPLL */
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FH_TOP_PLL10 = 10, /*ADSPPLL */
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FH_TOP_PLL11 = 11, /*IMGPLL */
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FH_TOP_PLL12 = 12, /*TVDPLL */
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FH_GPU_PLL0 = 13, /*MFGPLL1 */
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FH_GPU_PLL1 = 14, /*MFGPLL2 */
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FH_GPU_PLL2 = 15, /*MFGPLL3 */
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FH_GPU_PLL3 = 16, /*MFGPLL4 */
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FH_APU_PLL0 = 17, /*APUPLL */
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FH_APU_PLL1 = 18, /*NPUPLL */
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FH_APU_PLL2 = 19, /*APUPLL1 */
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FH_APU_PLL3 = 20, /*APUPLL2 */
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FH_PLL_NUM,
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};
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extern int mt_dfs_general_pll(unsigned int pll_id, unsigned int target_dds);
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/* for build pass only */
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struct freqhopping_ssc {
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unsigned int idx_pattern;
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unsigned int dt;
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unsigned int df;
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unsigned int upbnd;
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unsigned int lowbnd;
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unsigned int dds;
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};
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struct freqhopping_ioctl {
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unsigned int pll_id;
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struct freqhopping_ssc ssc_setting; /* used only when user-define */
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int result;
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};
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#endif /* !__MT_FREQHOPPING_H__ */
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