1106 lines
27 KiB
C
1106 lines
27 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Joey Pan <joey.pan@mediatek.com>
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*/
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#ifndef __LCM_DRV_H__
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#define __LCM_DRV_H__
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#if defined(CONFIG_SMCDSD_PANEL)
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#include "smcdsd_notify.h"
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#include "smcdsd_abd.h"
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extern unsigned int rx_offset;
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extern unsigned char data_type;
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extern unsigned int gpara_len;
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#endif
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#ifndef ARY_SIZE
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#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
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#endif
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/* ------------------------------------------------------------------------- */
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/* common enumerations */
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enum LCM_TYPE {
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LCM_TYPE_DBI = 0,
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LCM_TYPE_DPI,
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LCM_TYPE_DSI
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};
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enum LCM_CTRL {
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LCM_CTRL_NONE = 0,
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LCM_CTRL_SERIAL_DBI,
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LCM_CTRL_PARALLEL_DBI,
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LCM_CTRL_GPIO
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};
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enum LCM_POLARITY {
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LCM_POLARITY_RISING = 0,
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LCM_POLARITY_FALLING = 1
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};
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enum LCM_CLOCK_PHASE {
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LCM_CLOCK_PHASE_0 = 0,
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LCM_CLOCK_PHASE_90 = 1
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};
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enum LCM_COLOR_ORDER {
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LCM_COLOR_ORDER_RGB = 0,
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LCM_COLOR_ORDER_BGR = 1
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};
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enum LCM_DRIVING_CURRENT {
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LCM_DRIVING_CURRENT_DEFAULT,
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LCM_DRIVING_CURRENT_8MA = (1 << 0),
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LCM_DRIVING_CURRENT_4MA = (1 << 1),
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LCM_DRIVING_CURRENT_2MA = (1 << 2),
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LCM_DRIVING_CURRENT_SLEW_CNTL = (1 << 3),
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LCM_DRIVING_CURRENT_6575_4MA = (1 << 4),
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LCM_DRIVING_CURRENT_6575_8MA = (3 << 4),
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LCM_DRIVING_CURRENT_6575_12MA = (2 << 4),
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LCM_DRIVING_CURRENT_6575_16MA = (4 << 4),
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LCM_DRIVING_CURRENT_6MA,
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LCM_DRIVING_CURRENT_10MA,
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LCM_DRIVING_CURRENT_12MA,
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LCM_DRIVING_CURRENT_14MA,
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LCM_DRIVING_CURRENT_16MA,
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LCM_DRIVING_CURRENT_20MA,
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LCM_DRIVING_CURRENT_24MA,
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LCM_DRIVING_CURRENT_28MA,
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LCM_DRIVING_CURRENT_32MA
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};
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enum LCM_INTERFACE_ID {
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LCM_INTERFACE_NOTDEFINED = 0,
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LCM_INTERFACE_DSI0,
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LCM_INTERFACE_DSI1,
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LCM_INTERFACE_DSI_DUAL,
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LCM_INTERFACE_DPI0,
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LCM_INTERFACE_DPI1,
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LCM_INTERFACE_DBI0
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};
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enum LCM_IOCTL {
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LCM_IOCTL_NULL = 0,
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};
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enum LCM_Send_Cmd_Mode {
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LCM_SEND_IN_CMD = 0,
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LCM_SEND_IN_VDO
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};
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/* DBI related enumerations */
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enum LCM_DBI_CLOCK_FREQ {
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LCM_DBI_CLOCK_FREQ_104M = 0,
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LCM_DBI_CLOCK_FREQ_52M,
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LCM_DBI_CLOCK_FREQ_26M,
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LCM_DBI_CLOCK_FREQ_13M,
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LCM_DBI_CLOCK_FREQ_7M
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};
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enum LCM_DBI_DATA_WIDTH {
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LCM_DBI_DATA_WIDTH_8BITS = 0,
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LCM_DBI_DATA_WIDTH_9BITS = 1,
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LCM_DBI_DATA_WIDTH_16BITS = 2,
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LCM_DBI_DATA_WIDTH_18BITS = 3,
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LCM_DBI_DATA_WIDTH_24BITS = 4,
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LCM_DBI_DATA_WIDTH_32BITS = 5
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};
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enum LCM_DBI_CPU_WRITE_BITS {
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LCM_DBI_CPU_WRITE_8_BITS = 8,
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LCM_DBI_CPU_WRITE_16_BITS = 16,
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LCM_DBI_CPU_WRITE_32_BITS = 32,
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};
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enum LCM_DBI_FORMAT {
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LCM_DBI_FORMAT_RGB332 = 0,
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LCM_DBI_FORMAT_RGB444 = 1,
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LCM_DBI_FORMAT_RGB565 = 2,
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LCM_DBI_FORMAT_RGB666 = 3,
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LCM_DBI_FORMAT_RGB888 = 4
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};
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enum LCM_DBI_TRANS_SEQ {
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LCM_DBI_TRANS_SEQ_MSB_FIRST = 0,
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LCM_DBI_TRANS_SEQ_LSB_FIRST = 1
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};
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enum LCM_DBI_PADDING {
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LCM_DBI_PADDING_ON_LSB = 0,
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LCM_DBI_PADDING_ON_MSB = 1
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};
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enum LCM_DBI_TE_MODE {
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LCM_DBI_TE_MODE_DISABLED = 0,
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LCM_DBI_TE_MODE_VSYNC_ONLY = 1,
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LCM_DBI_TE_MODE_VSYNC_OR_HSYNC = 2,
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};
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enum LCM_DBI_TE_VS_WIDTH_CNT_DIV {
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LCM_DBI_TE_VS_WIDTH_CNT_DIV_8 = 0,
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LCM_DBI_TE_VS_WIDTH_CNT_DIV_16 = 1,
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LCM_DBI_TE_VS_WIDTH_CNT_DIV_32 = 2,
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LCM_DBI_TE_VS_WIDTH_CNT_DIV_64 = 3,
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};
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/* DPI related enumerations */
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enum LCM_DPI_FORMAT {
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LCM_DPI_FORMAT_RGB565 = 0,
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LCM_DPI_FORMAT_RGB666 = 1,
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LCM_DPI_FORMAT_RGB888 = 2
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};
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enum LCM_SERIAL_CLOCK_FREQ {
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LCM_SERIAL_CLOCK_FREQ_104M = 0,
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LCM_SERIAL_CLOCK_FREQ_26M,
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LCM_SERIAL_CLOCK_FREQ_52M
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};
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enum LCM_SERIAL_CLOCK_DIV {
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LCM_SERIAL_CLOCK_DIV_2 = 0,
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LCM_SERIAL_CLOCK_DIV_4 = 1,
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LCM_SERIAL_CLOCK_DIV_8 = 2,
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LCM_SERIAL_CLOCK_DIV_16 = 3,
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};
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/* DSI related enumerations */
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enum LCM_DSI_MODE_CON {
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CMD_MODE = 0,
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SYNC_PULSE_VDO_MODE = 1,
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SYNC_EVENT_VDO_MODE = 2,
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BURST_VDO_MODE = 3
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};
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enum LCM_LANE_NUM {
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LCM_ONE_LANE = 1,
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LCM_TWO_LANE = 2,
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LCM_THREE_LANE = 3,
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LCM_FOUR_LANE = 4,
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};
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enum LCM_DSI_FORMAT {
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LCM_DSI_FORMAT_RGB565 = 0,
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LCM_DSI_FORMAT_RGB666_LOOSELY = 1,
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LCM_DSI_FORMAT_RGB666 = 2,
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LCM_DSI_FORMAT_RGB888 = 3,
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LCM_DSI_FORMAT_RGB101010 = 4,
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};
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enum LCM_DSI_TRANS_SEQ {
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LCM_DSI_TRANS_SEQ_MSB_FIRST = 0,
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LCM_DSI_TRANS_SEQ_LSB_FIRST = 1
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};
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enum LCM_DSI_PADDING {
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LCM_DSI_PADDING_ON_LSB = 0,
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LCM_DSI_PADDING_ON_MSB = 1
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};
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enum LCM_PS_TYPE {
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LCM_PACKED_PS_16BIT_RGB565 = 0,
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LCM_LOOSELY_PS_18BIT_RGB666 = 1,
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LCM_PACKED_PS_24BIT_RGB888 = 2,
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LCM_PACKED_PS_18BIT_RGB666 = 3
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};
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enum LCM_SCALE_TYPE {
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LCM_Hx1_Vx1 = 0,
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LCM_Hx1_Vx2 = 1,
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LCM_Hx2_Vx1 = 2,
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LCM_Hx2_Vx2 = 3
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};
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enum LCM_DSI_PLL_CLOCK {
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LCM_DSI_6589_PLL_CLOCK_NULL = 0,
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LCM_DSI_6589_PLL_CLOCK_201_5 = 1,
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LCM_DSI_6589_PLL_CLOCK_208 = 2,
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LCM_DSI_6589_PLL_CLOCK_214_5 = 3,
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LCM_DSI_6589_PLL_CLOCK_221 = 4,
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LCM_DSI_6589_PLL_CLOCK_227_5 = 5,
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LCM_DSI_6589_PLL_CLOCK_234 = 6,
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LCM_DSI_6589_PLL_CLOCK_240_5 = 7,
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LCM_DSI_6589_PLL_CLOCK_247 = 8,
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LCM_DSI_6589_PLL_CLOCK_253_5 = 9,
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LCM_DSI_6589_PLL_CLOCK_260 = 10,
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LCM_DSI_6589_PLL_CLOCK_266_5 = 11,
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LCM_DSI_6589_PLL_CLOCK_273 = 12,
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LCM_DSI_6589_PLL_CLOCK_279_5 = 13,
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LCM_DSI_6589_PLL_CLOCK_286 = 14,
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LCM_DSI_6589_PLL_CLOCK_292_5 = 15,
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LCM_DSI_6589_PLL_CLOCK_299 = 16,
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LCM_DSI_6589_PLL_CLOCK_305_5 = 17,
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LCM_DSI_6589_PLL_CLOCK_312 = 18,
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LCM_DSI_6589_PLL_CLOCK_318_5 = 19,
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LCM_DSI_6589_PLL_CLOCK_325 = 20,
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LCM_DSI_6589_PLL_CLOCK_331_5 = 21,
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LCM_DSI_6589_PLL_CLOCK_338 = 22,
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LCM_DSI_6589_PLL_CLOCK_344_5 = 23,
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LCM_DSI_6589_PLL_CLOCK_351 = 24,
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LCM_DSI_6589_PLL_CLOCK_357_5 = 25,
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LCM_DSI_6589_PLL_CLOCK_364 = 26,
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LCM_DSI_6589_PLL_CLOCK_370_5 = 27,
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LCM_DSI_6589_PLL_CLOCK_377 = 28,
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LCM_DSI_6589_PLL_CLOCK_383_5 = 29,
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LCM_DSI_6589_PLL_CLOCK_390 = 30,
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LCM_DSI_6589_PLL_CLOCK_396_5 = 31,
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LCM_DSI_6589_PLL_CLOCK_403 = 32,
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LCM_DSI_6589_PLL_CLOCK_409_5 = 33,
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LCM_DSI_6589_PLL_CLOCK_416 = 34,
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LCM_DSI_6589_PLL_CLOCK_422_5 = 35,
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LCM_DSI_6589_PLL_CLOCK_429 = 36,
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LCM_DSI_6589_PLL_CLOCK_435_5 = 37,
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LCM_DSI_6589_PLL_CLOCK_442 = 38,
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LCM_DSI_6589_PLL_CLOCK_448_5 = 39,
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LCM_DSI_6589_PLL_CLOCK_455 = 40,
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LCM_DSI_6589_PLL_CLOCK_461_5 = 41,
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LCM_DSI_6589_PLL_CLOCK_468 = 42,
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LCM_DSI_6589_PLL_CLOCK_474_5 = 43,
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LCM_DSI_6589_PLL_CLOCK_481 = 44,
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LCM_DSI_6589_PLL_CLOCK_487_5 = 45,
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LCM_DSI_6589_PLL_CLOCK_494 = 46,
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LCM_DSI_6589_PLL_CLOCK_500_5 = 47,
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LCM_DSI_6589_PLL_CLOCK_507 = 48,
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LCM_DSI_6589_PLL_CLOCK_513_5 = 49,
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LCM_DSI_6589_PLL_CLOCK_520 = 50,
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};
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/* ------------------------------------------------------------------------- */
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struct LCM_DBI_DATA_FORMAT {
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enum LCM_COLOR_ORDER color_order;
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enum LCM_DBI_TRANS_SEQ trans_seq;
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enum LCM_DBI_PADDING padding;
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enum LCM_DBI_FORMAT format;
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enum LCM_DBI_DATA_WIDTH width;
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};
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struct LCM_DBI_SERIAL_PARAMS {
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enum LCM_POLARITY cs_polarity;
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enum LCM_POLARITY clk_polarity;
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enum LCM_CLOCK_PHASE clk_phase;
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unsigned int is_non_dbi_mode;
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enum LCM_SERIAL_CLOCK_FREQ clock_base;
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enum LCM_SERIAL_CLOCK_DIV clock_div;
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unsigned int css;
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unsigned int csh;
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unsigned int rd_1st;
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unsigned int rd_2nd;
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unsigned int wr_1st;
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unsigned int wr_2nd;
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unsigned int sif_3wire;
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unsigned int sif_sdi;
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enum LCM_POLARITY sif_1st_pol;
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enum LCM_POLARITY sif_sck_def;
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unsigned int sif_div2;
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unsigned int sif_hw_cs;
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/* ////////////////////////////////// */
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};
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struct LCM_DBI_PARALLEL_PARAMS {
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/* timing parameters */
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unsigned int write_setup;
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unsigned int write_hold;
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unsigned int write_wait;
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unsigned int read_setup;
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unsigned int read_hold;
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unsigned int read_latency;
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unsigned int wait_period;
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/*only for 6575 */
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unsigned int cs_high_width;
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};
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struct LCM_DSI_DATA_FORMAT {
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enum LCM_COLOR_ORDER color_order;
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enum LCM_DSI_TRANS_SEQ trans_seq;
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enum LCM_DSI_PADDING padding;
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enum LCM_DSI_FORMAT format;
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};
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struct LCM_DSI_MODE_SWITCH_CMD {
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enum LCM_DSI_MODE_CON mode;
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unsigned int cmd_if;
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unsigned int addr;
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unsigned int val[4];
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};
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struct LCM_UFOE_CONFIG_PARAMS {
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unsigned int compress_ratio;
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unsigned int lr_mode_en;
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unsigned int vlc_disable;
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unsigned int vlc_config;
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};
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_MTK_MT6382_BDG
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struct LCM_DSC_CONFIG_PARAMS {
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unsigned int ver; /* [7:4] major [3:0] minor */
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unsigned int slice_width;
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unsigned int bit_per_pixel;
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unsigned int slice_mode;
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unsigned int rgb_swap;
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unsigned int dsc_cfg;
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unsigned int dsc_line_buf_depth;
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unsigned int bit_per_channel;
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unsigned int rct_on;
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unsigned int bp_enable;
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unsigned int pic_height; /* need to check */
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unsigned int pic_width; /* need to check */
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unsigned int slice_height;
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unsigned int chunk_size;
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unsigned int dec_delay;
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unsigned int xmit_delay;
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unsigned int scale_value;
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unsigned int increment_interval;
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unsigned int line_bpg_offset;
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unsigned int decrement_interval;
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unsigned int nfl_bpg_offset;
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unsigned int slice_bpg_offset;
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unsigned int initial_offset;
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unsigned int final_offset;
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unsigned int flatness_minqp;
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unsigned int flatness_maxqp;
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unsigned int rc_model_size;
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unsigned int rc_edge_factor;
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unsigned int rc_quant_incr_limit0;
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unsigned int rc_quant_incr_limit1;
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unsigned int rc_tgt_offset_hi;
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unsigned int rc_tgt_offset_lo;
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};
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#else
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struct LCM_DSC_CONFIG_PARAMS {
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unsigned int slice_width;
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unsigned int slice_hight;
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unsigned int bit_per_pixel;
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unsigned int slice_mode;
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unsigned int rgb_swap;
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unsigned int dsc_cfg;
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unsigned int dsc_line_buf_depth;
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unsigned int bit_per_channel;
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unsigned int rct_on;
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unsigned int bp_enable;
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unsigned int dec_delay;
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unsigned int xmit_delay;
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unsigned int scale_value;
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unsigned int increment_interval;
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unsigned int line_bpg_offset;
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unsigned int decrement_interval;
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unsigned int nfl_bpg_offset;
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unsigned int slice_bpg_offset;
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unsigned int initial_offset;
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unsigned int final_offset;
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unsigned int flatness_minqp;
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unsigned int flatness_maxqp;
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unsigned int rc_mode1_size;
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};
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#endif
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struct LCM_DBI_PARAMS {
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/* common parameters for serial & parallel interface */
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unsigned int port;
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enum LCM_DBI_CLOCK_FREQ clock_freq;
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enum LCM_DBI_DATA_WIDTH data_width;
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struct LCM_DBI_DATA_FORMAT data_format;
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enum LCM_DBI_CPU_WRITE_BITS cpu_write_bits;
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enum LCM_DRIVING_CURRENT io_driving_current;
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enum LCM_DRIVING_CURRENT msb_io_driving_current;
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enum LCM_DRIVING_CURRENT ctrl_io_driving_current;
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/* tearing control */
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enum LCM_DBI_TE_MODE te_mode;
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enum LCM_POLARITY te_edge_polarity;
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unsigned int te_hs_delay_cnt;
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unsigned int te_vs_width_cnt;
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enum LCM_DBI_TE_VS_WIDTH_CNT_DIV te_vs_width_cnt_div;
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/* particular parameters for serial & parallel interface */
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struct LCM_DBI_SERIAL_PARAMS serial;
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struct LCM_DBI_PARALLEL_PARAMS parallel;
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};
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struct LCM_DPI_PARAMS {
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/* Pixel Clock Frequency = 26MHz * mipi_pll_clk_div1*/
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/* / (mipi_pll_clk_ref + 1)*/
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/* / (2 * mipi_pll_clk_div2)*/
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/* / dpi_clk_div */
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unsigned int mipi_pll_clk_ref; /* 0..1 */
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unsigned int mipi_pll_clk_div1; /* 0..63 */
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unsigned int mipi_pll_clk_div2; /* 0..15 */
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/* PCLK=> 8: 26MHz, 10: 35MHz, 12: 40MHz */
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unsigned int mipi_pll_clk_fbk_div;
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unsigned int dpi_clk_div; /* 2..32 */
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unsigned int dpi_clk_duty; /* (dpi_clk_div - 1) .. 31 */
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unsigned int PLL_CLOCK;
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unsigned int dpi_clock;
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unsigned int ssc_disable;
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unsigned int ssc_range;
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unsigned int width;
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unsigned int height;
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unsigned int bg_width;
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unsigned int bg_height;
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/* polarity parameters */
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enum LCM_POLARITY clk_pol;
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enum LCM_POLARITY de_pol;
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enum LCM_POLARITY vsync_pol;
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enum LCM_POLARITY hsync_pol;
|
|
|
|
/* timing parameters */
|
|
unsigned int hsync_pulse_width;
|
|
unsigned int hsync_back_porch;
|
|
unsigned int hsync_front_porch;
|
|
unsigned int vsync_pulse_width;
|
|
unsigned int vsync_back_porch;
|
|
unsigned int vsync_front_porch;
|
|
|
|
/* output format parameters */
|
|
enum LCM_DPI_FORMAT format;
|
|
enum LCM_COLOR_ORDER rgb_order;
|
|
unsigned int is_serial_output;
|
|
unsigned int i2x_en;
|
|
unsigned int i2x_edge;
|
|
unsigned int embsync;
|
|
unsigned int lvds_tx_en;
|
|
unsigned int bit_swap;
|
|
unsigned int is_dual_lvds_tx;
|
|
unsigned int is_vesa;
|
|
/* intermediate buffers parameters */
|
|
unsigned int intermediat_buffer_num; /* 2..3 */
|
|
|
|
unsigned int dsc_enable;
|
|
struct LCM_DSC_CONFIG_PARAMS dsc_params;
|
|
|
|
/* iopad parameters */
|
|
enum LCM_DRIVING_CURRENT io_driving_current;
|
|
enum LCM_DRIVING_CURRENT msb_io_driving_current;
|
|
enum LCM_DRIVING_CURRENT lsb_io_driving_current;
|
|
enum LCM_DRIVING_CURRENT ctrl_io_driving_current;
|
|
};
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
#define RT_MAX_NUM 10
|
|
#define ESD_CHECK_NUM 3
|
|
struct LCM_esd_check_item {
|
|
unsigned char cmd;
|
|
unsigned char count;
|
|
unsigned char para_list[RT_MAX_NUM];
|
|
};
|
|
enum DUAL_DSI_TYPE {
|
|
DUAL_DSI_NONE = 0x0,
|
|
DUAL_DSI_CMD = 0x1,
|
|
DUAL_DSI_VDO = 0x2,
|
|
};
|
|
|
|
enum MIPITX_PHY_LANE_SWAP {
|
|
MIPITX_PHY_LANE_0 = 0,
|
|
MIPITX_PHY_LANE_1,
|
|
MIPITX_PHY_LANE_2,
|
|
MIPITX_PHY_LANE_3,
|
|
MIPITX_PHY_LANE_CK,
|
|
MIPITX_PHY_LANE_RX,
|
|
MIPITX_PHY_LANE_NUM
|
|
};
|
|
|
|
enum MIPITX_PHY_PORT {
|
|
MIPITX_PHY_PORT_0 = 0,
|
|
MIPITX_PHY_PORT_1,
|
|
MIPITX_PHY_PORT_NUM
|
|
};
|
|
|
|
/*ARR*/
|
|
#define DYNAMIC_FPS_LEVELS 10
|
|
struct dynamic_fps_info {
|
|
unsigned int fps;
|
|
unsigned int vfp; /*lines*/
|
|
/*unsigned int idle_check_interval;*//*ms*/
|
|
};
|
|
|
|
struct vsync_trigger_time {
|
|
unsigned int fps;
|
|
unsigned int trigger_after_te;
|
|
unsigned int config_expense_time;
|
|
};
|
|
|
|
/*DynFPS*/
|
|
enum DynFPS_LEVEL {
|
|
DFPS_LEVEL0 = 0,
|
|
DFPS_LEVEL1,
|
|
DFPS_LEVELNUM,
|
|
};
|
|
|
|
#define DFPS_LEVELS 2
|
|
enum FPS_CHANGE_INDEX {
|
|
DYNFPS_NOT_DEFINED = 0,
|
|
DYNFPS_DSI_VFP = 1,
|
|
DYNFPS_DSI_HFP = 2,
|
|
DYNFPS_DSI_MIPI_CLK = 4,
|
|
};
|
|
|
|
struct dfps_info {
|
|
enum DynFPS_LEVEL level;
|
|
unsigned int fps; /*real fps *100*/
|
|
|
|
unsigned int vertical_sync_active;
|
|
unsigned int vertical_backporch;
|
|
unsigned int vertical_frontporch;
|
|
unsigned int vertical_frontporch_for_low_power;
|
|
|
|
unsigned int horizontal_sync_active;
|
|
unsigned int horizontal_backporch;
|
|
unsigned int horizontal_frontporch;
|
|
|
|
unsigned int PLL_CLOCK;
|
|
/* data_rate = PLL_CLOCK x 2 */
|
|
unsigned int data_rate;
|
|
/*real fps during active*/
|
|
unsigned int vact_timing_fps; /*real vact timing fps * 100*/
|
|
|
|
/*mipi hopping*/
|
|
unsigned int dynamic_switch_mipi;
|
|
unsigned int vertical_sync_active_dyn;
|
|
unsigned int vertical_backporch_dyn;
|
|
unsigned int vertical_frontporch_dyn;
|
|
unsigned int vertical_frontporch_for_low_power_dyn;
|
|
unsigned int vertical_active_line_dyn;
|
|
|
|
unsigned int horizontal_sync_active_dyn;
|
|
unsigned int horizontal_backporch_dyn;
|
|
unsigned int horizontal_frontporch_dyn;
|
|
unsigned int horizontal_active_pixel_dyn;
|
|
|
|
unsigned int PLL_CLOCK_dyn; /* PLL_CLOCK = (int) PLL_CLOCK */
|
|
unsigned int data_rate_dyn; /* data_rate = PLL_CLOCK x 2 */
|
|
|
|
/*real fps during active*/
|
|
unsigned int vact_timing_fps_dyn;
|
|
};
|
|
|
|
|
|
struct LCM_DSI_PARAMS {
|
|
enum LCM_DSI_MODE_CON mode;
|
|
enum LCM_DSI_MODE_CON switch_mode;
|
|
unsigned int DSI_WMEM_CONTI;
|
|
unsigned int DSI_RMEM_CONTI;
|
|
unsigned int VC_NUM;
|
|
|
|
enum LCM_LANE_NUM LANE_NUM;
|
|
struct LCM_DSI_DATA_FORMAT data_format;
|
|
|
|
/* intermediate buffers parameters */
|
|
unsigned int intermediat_buffer_num; /* 2..3 */
|
|
|
|
enum LCM_PS_TYPE PS;
|
|
unsigned int word_count;
|
|
|
|
unsigned int packet_size;
|
|
unsigned int packet_size_mult;
|
|
unsigned int vertical_sync_active;
|
|
unsigned int vertical_backporch;
|
|
unsigned int vertical_frontporch;
|
|
unsigned int vertical_frontporch_for_low_power;
|
|
unsigned int vertical_active_line;
|
|
|
|
unsigned int horizontal_sync_active;
|
|
unsigned int horizontal_backporch;
|
|
unsigned int horizontal_frontporch;
|
|
unsigned int horizontal_blanking_pixel;
|
|
unsigned int horizontal_active_pixel;
|
|
unsigned int horizontal_bllp;
|
|
|
|
unsigned int line_byte;
|
|
unsigned int horizontal_sync_active_byte;
|
|
unsigned int horizontal_backporch_byte;
|
|
unsigned int horizontal_frontporch_byte;
|
|
unsigned int rgb_byte;
|
|
|
|
unsigned int horizontal_sync_active_word_count;
|
|
unsigned int horizontal_backporch_word_count;
|
|
unsigned int horizontal_frontporch_word_count;
|
|
|
|
unsigned char HS_TRAIL;
|
|
unsigned char HS_ZERO;
|
|
unsigned char HS_PRPR;
|
|
unsigned char LPX;
|
|
|
|
unsigned char TA_SACK;
|
|
unsigned char TA_GET;
|
|
unsigned char TA_SURE;
|
|
unsigned char TA_GO;
|
|
|
|
unsigned char CLK_TRAIL;
|
|
unsigned char CLK_ZERO;
|
|
unsigned char LPX_WAIT;
|
|
unsigned char CONT_DET;
|
|
|
|
unsigned char CLK_HS_PRPR;
|
|
unsigned char CLK_HS_POST;
|
|
unsigned char DA_HS_EXIT;
|
|
unsigned char CLK_HS_EXIT;
|
|
|
|
unsigned int pll_select;
|
|
unsigned int pll_div1;
|
|
unsigned int pll_div2;
|
|
unsigned int fbk_div;
|
|
|
|
unsigned int pll_prediv;
|
|
unsigned int pll_posdiv;
|
|
unsigned int pll_s2qdiv;
|
|
|
|
unsigned int fbk_sel;
|
|
unsigned int rg_bir;
|
|
unsigned int rg_bic;
|
|
unsigned int rg_bp;
|
|
/* PLL_CLOCK = (int) PLL_CLOCK */
|
|
unsigned int PLL_CLOCK;
|
|
/* data_rate = PLL_CLOCK x 2 */
|
|
unsigned int data_rate;
|
|
unsigned int PLL_CK_VDO;
|
|
unsigned int PLL_CK_CMD;
|
|
unsigned int dsi_clock;
|
|
unsigned int ssc_disable;
|
|
unsigned int ssc_range;
|
|
unsigned int compatibility_for_nvk;
|
|
unsigned int cont_clock;
|
|
unsigned int ufoe_enable;
|
|
unsigned int dsc_enable;
|
|
unsigned int bdg_dsc_enable;
|
|
unsigned int bdg_ssc_disable;
|
|
struct LCM_UFOE_CONFIG_PARAMS ufoe_params;
|
|
struct LCM_DSC_CONFIG_PARAMS dsc_params;
|
|
unsigned int edp_panel;
|
|
unsigned int customization_esd_check_enable;
|
|
unsigned int esd_check_enable;
|
|
unsigned int lcm_int_te_monitor;
|
|
unsigned int lcm_int_te_period;
|
|
|
|
unsigned int lcm_ext_te_monitor;
|
|
unsigned int lcm_ext_te_enable;
|
|
|
|
unsigned int noncont_clock;
|
|
unsigned int noncont_clock_period;
|
|
unsigned int clk_lp_per_line_enable;
|
|
struct LCM_esd_check_item lcm_esd_check_table[ESD_CHECK_NUM];
|
|
unsigned int switch_mode_enable;
|
|
enum DUAL_DSI_TYPE dual_dsi_type;
|
|
unsigned int lane_swap_en;
|
|
enum MIPITX_PHY_LANE_SWAP
|
|
lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
|
|
|
|
unsigned int vertical_vfp_lp;
|
|
unsigned int PLL_CLOCK_lp;
|
|
unsigned int ulps_sw_enable;
|
|
unsigned int null_packet_en;
|
|
unsigned int mixmode_enable;
|
|
unsigned int mixmode_mipi_clock;
|
|
unsigned int pwm_fps;
|
|
unsigned int send_frame_enable;
|
|
|
|
unsigned int lfr_enable;
|
|
unsigned int lfr_mode;
|
|
unsigned int lfr_type;
|
|
unsigned int lfr_skip_num;
|
|
|
|
unsigned int ext_te_edge;
|
|
unsigned int eint_disable;
|
|
|
|
unsigned int IsCphy;
|
|
unsigned int PHY_SEL0;
|
|
unsigned int PHY_SEL1;
|
|
unsigned int PHY_SEL2;
|
|
unsigned int PHY_SEL3;
|
|
|
|
unsigned int dynamic_switch_mipi;
|
|
unsigned int vertical_sync_active_dyn;
|
|
unsigned int vertical_backporch_dyn;
|
|
unsigned int vertical_frontporch_dyn;
|
|
unsigned int vertical_active_line_dyn;
|
|
|
|
unsigned int horizontal_sync_active_dyn;
|
|
unsigned int horizontal_backporch_dyn;
|
|
unsigned int horizontal_frontporch_dyn;
|
|
unsigned int horizontal_active_pixel_dyn;
|
|
|
|
unsigned int PLL_CLOCK_dyn; /* PLL_CLOCK = (int) PLL_CLOCK */
|
|
unsigned int data_rate_dyn; /* data_rate = PLL_CLOCK x 2 */
|
|
|
|
/*for ARR*/
|
|
unsigned int dynamic_fps_levels;
|
|
struct dynamic_fps_info dynamic_fps_table[DYNAMIC_FPS_LEVELS];
|
|
struct vsync_trigger_time vsync_after_te[DFPS_LEVELS];
|
|
|
|
#ifdef CONFIG_MTK_HIGH_FRAME_RATE
|
|
/****DynFPS start****/
|
|
unsigned int dfps_enable;
|
|
unsigned int dfps_default_fps;
|
|
unsigned int dfps_def_vact_tim_fps;
|
|
unsigned int dfps_num;
|
|
/*unsigned int dfps_solution;*/
|
|
struct dfps_info dfps_params[DFPS_LEVELS];
|
|
/****DynFPS end****/
|
|
#endif
|
|
};
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
struct LCM_PARAMS {
|
|
enum LCM_TYPE type;
|
|
enum LCM_CTRL ctrl; /* ! how to control LCM registers */
|
|
enum LCM_INTERFACE_ID lcm_if;
|
|
enum LCM_INTERFACE_ID lcm_cmd_if;
|
|
/* common parameters */
|
|
unsigned int lcm_x;
|
|
unsigned int lcm_y;
|
|
unsigned int width;
|
|
unsigned int height;
|
|
unsigned int virtual_width;
|
|
unsigned int virtual_height;
|
|
unsigned int density;
|
|
/* DBI or DPI should select IO mode according to chip spec */
|
|
unsigned int io_select_mode;
|
|
|
|
/* particular parameters */
|
|
struct LCM_DBI_PARAMS dbi;
|
|
struct LCM_DPI_PARAMS dpi;
|
|
struct LCM_DSI_PARAMS dsi;
|
|
unsigned int physical_width; /* length: mm, for legacy use */
|
|
unsigned int physical_height; /* length: mm, for legacy use */
|
|
/* length: um, for more precise precision */
|
|
unsigned int physical_width_um;
|
|
unsigned int physical_height_um;
|
|
unsigned int od_table_size;
|
|
void *od_table;
|
|
unsigned int max_refresh_rate;
|
|
unsigned int min_refresh_rate;
|
|
|
|
unsigned int round_corner_en;
|
|
unsigned int full_content;
|
|
unsigned int corner_pattern_width;
|
|
unsigned int corner_pattern_height;
|
|
unsigned int corner_pattern_height_bot;
|
|
unsigned int corner_pattern_tp_size;
|
|
void *corner_pattern_lt_addr;
|
|
|
|
int lcm_color_mode;
|
|
unsigned int min_luminance;
|
|
unsigned int average_luminance;
|
|
unsigned int max_luminance;
|
|
|
|
#ifdef CONFIG_MTK_HIGH_FRAME_RATE
|
|
enum LCM_Send_Cmd_Mode sendmode;
|
|
#endif
|
|
|
|
unsigned int hbm_en_time;
|
|
unsigned int hbm_dis_time;
|
|
};
|
|
|
|
|
|
#ifndef MAX
|
|
#define MAX(x, y) (((x) >= (y)) ? (x) : (y))
|
|
#endif /* MAX */
|
|
|
|
#ifndef MIN
|
|
#define MIN(x, y) (((x) <= (y)) ? (x) : (y))
|
|
#endif /* MIN */
|
|
|
|
#define INIT_SIZE (640)
|
|
#define COMPARE_ID_SIZE (32)
|
|
#define SUSPEND_SIZE (32)
|
|
#define BACKLIGHT_SIZE (32)
|
|
#define BACKLIGHT_CMDQ_SIZE (32)
|
|
#define MAX_SIZE (MAX(MAX(MAX(MAX(INIT_SIZE, COMPARE_ID_SIZE), \
|
|
SUSPEND_SIZE), BACKLIGHT_SIZE), BACKLIGHT_CMDQ_SIZE))
|
|
|
|
|
|
struct LCM_DATA_T1 {
|
|
char data;
|
|
char padding[131];
|
|
};
|
|
|
|
|
|
struct LCM_DATA_T2 {
|
|
char cmd;
|
|
char data;
|
|
char padding[130];
|
|
};
|
|
|
|
|
|
struct LCM_DATA_T3 {
|
|
char cmd;
|
|
char size;
|
|
char data[128];
|
|
char padding[2];
|
|
};
|
|
|
|
|
|
struct LCM_DATA_T4 {
|
|
char cmd;
|
|
char location;
|
|
char data;
|
|
char padding[129];
|
|
};
|
|
|
|
|
|
struct LCM_DATA_T5 {
|
|
char size;
|
|
char cmd[128];
|
|
char padding[3];
|
|
};
|
|
|
|
|
|
struct LCM_DATA {
|
|
char func;
|
|
char type;
|
|
char size;
|
|
char padding;
|
|
|
|
union {
|
|
struct LCM_DATA_T1 data_t1;
|
|
struct LCM_DATA_T2 data_t2;
|
|
struct LCM_DATA_T3 data_t3;
|
|
struct LCM_DATA_T4 data_t4;
|
|
struct LCM_DATA_T5 data_t5;
|
|
};
|
|
};
|
|
|
|
|
|
struct LCM_DTS {
|
|
unsigned int parsing;
|
|
unsigned int id;
|
|
unsigned int init_size;
|
|
unsigned int compare_id_size;
|
|
unsigned int suspend_size;
|
|
unsigned int backlight_size;
|
|
unsigned int backlight_cmdq_size;
|
|
|
|
struct LCM_PARAMS params;
|
|
struct LCM_DATA init[INIT_SIZE];
|
|
struct LCM_DATA compare_id[COMPARE_ID_SIZE];
|
|
struct LCM_DATA suspend[SUSPEND_SIZE];
|
|
struct LCM_DATA backlight[BACKLIGHT_SIZE];
|
|
struct LCM_DATA backlight_cmdq[BACKLIGHT_CMDQ_SIZE];
|
|
};
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
#define REGFLAG_ESCAPE_ID (0x00)
|
|
#define REGFLAG_DELAY_MS_V3 (0xFF)
|
|
|
|
struct LCM_setting_table_V3 {
|
|
unsigned char id;
|
|
unsigned char cmd;
|
|
unsigned int count;
|
|
unsigned char para_list[512];
|
|
};
|
|
|
|
/*
|
|
* dtype ---- data type
|
|
* vc ---- virtual channel
|
|
* dlen ---- data length
|
|
* link_state ---- HS:0 LP:1
|
|
* payload ---- payload
|
|
*/
|
|
struct dsi_cmd_desc {
|
|
unsigned int dtype;
|
|
unsigned int vc;
|
|
unsigned int dlen;
|
|
unsigned int link_state;
|
|
unsigned int cmd;
|
|
char *payload;
|
|
};
|
|
|
|
struct LCM_UTIL_FUNCS {
|
|
void (*set_reset_pin)(unsigned int value);
|
|
void (*set_chip_select)(unsigned int value);
|
|
int (*set_gpio_out)(unsigned int gpio, unsigned int value);
|
|
void (*set_te_pin)(void);
|
|
|
|
void (*udelay)(unsigned int us);
|
|
void (*mdelay)(unsigned int ms);
|
|
void (*rar)(unsigned int ms);
|
|
|
|
void (*send_cmd)(unsigned int cmd);
|
|
void (*send_data)(unsigned int data);
|
|
unsigned int (*read_data)(void);
|
|
|
|
void (*dsi_set_cmdq_V3)(struct LCM_setting_table_V3 *para_list,
|
|
unsigned int size, unsigned char force_update);
|
|
void (*dsi_set_cmdq_V2)(unsigned int cmd, unsigned int count,
|
|
unsigned char *para_list, unsigned char force_update);
|
|
void (*dsi_set_cmdq)(unsigned int *pdata, unsigned int queue_size,
|
|
unsigned char force_update);
|
|
void (*dsi_set_null)(unsigned int cmd, unsigned int count,
|
|
unsigned char *para_list, unsigned char force_update);
|
|
void (*dsi_write_cmd)(unsigned int cmd);
|
|
void (*dsi_write_regs)(unsigned int addr, unsigned int *para,
|
|
unsigned int nums);
|
|
unsigned int (*dsi_read_reg)(void);
|
|
unsigned int (*dsi_dcs_read_lcm_reg)(unsigned char cmd);
|
|
unsigned int (*dsi_dcs_read_lcm_reg_v2)(unsigned char cmd,
|
|
unsigned char *buffer, unsigned char buffer_size);
|
|
void (*wait_transfer_done)(void);
|
|
|
|
/* FIXME: GPIO mode should not be configured in lcm driver*/
|
|
/* REMOVE ME after GPIO customization is done */
|
|
int (*set_gpio_mode)(unsigned int pin, unsigned int mode);
|
|
int (*set_gpio_dir)(unsigned int pin, unsigned int dir);
|
|
int (*set_gpio_pull_enable)(unsigned int pin, unsigned char pull_en);
|
|
long (*set_gpio_lcd_enp_bias)(unsigned int value);
|
|
void (*dsi_set_cmdq_V11)(void *cmdq, unsigned int *pdata,
|
|
unsigned int queue_size, unsigned char force_update);
|
|
void (*dsi_set_cmdq_V22)(void *cmdq, unsigned int cmd,
|
|
unsigned int count, unsigned char *para_list,
|
|
unsigned char force_update);
|
|
void (*dsi_swap_port)(int swap);
|
|
void (*dsi_set_cmdq_V23)(void *cmdq, unsigned int cmd,
|
|
unsigned int count, unsigned char *para_list,
|
|
unsigned char force_update); /* dual */
|
|
void (*mipi_dsi_cmds_tx)(void *cmdq, struct dsi_cmd_desc *cmds);
|
|
unsigned int (*mipi_dsi_cmds_rx)(char *out,
|
|
struct dsi_cmd_desc *cmds, unsigned int len);
|
|
/*Dynfps*/
|
|
void (*dsi_dynfps_send_cmd)(
|
|
void *cmdq, unsigned int cmd,
|
|
unsigned int count, unsigned char *para_list,
|
|
unsigned char force_update, enum LCM_Send_Cmd_Mode sendmode);
|
|
|
|
};
|
|
enum LCM_DRV_IOCTL_CMD {
|
|
LCM_DRV_IOCTL_ENABLE_CMD_MODE = 0x100,
|
|
};
|
|
|
|
struct LCM_DRIVER {
|
|
const char *name;
|
|
void (*set_util_funcs)(const struct LCM_UTIL_FUNCS *util);
|
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void (*get_params)(struct LCM_PARAMS *params);
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void (*init)(void);
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void (*suspend)(void);
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void (*resume)(void);
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/* for power-on sequence refinement */
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void (*init_power)(void);
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void (*suspend_power)(void);
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void (*resume_power)(void);
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#if defined(CONFIG_SMCDSD_PANEL)
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void (*cmdq)(unsigned int enable);
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void (*power_enable)(unsigned int enable);
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void (*disable)(void);
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bool (*path_lock)(bool en);
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bool (*framedone_notify)(void);
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#endif
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void (*update)(unsigned int x, unsigned int y, unsigned int width,
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unsigned int height);
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unsigned int (*compare_id)(void);
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void (*parse_dts)(const struct LCM_DTS *DTS,
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unsigned char force_update);
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/* /////////////////////////CABC backlight related function */
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void (*set_backlight)(unsigned int level);
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void (*set_backlight_cmdq)(void *handle, unsigned int level);
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bool (*get_hbm_state)(void);
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bool (*get_hbm_wait)(void);
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bool (*set_hbm_wait)(bool wait);
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bool (*set_hbm_cmdq)(bool en, void *qhandle);
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void (*set_pwm)(unsigned int divider);
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unsigned int (*get_pwm)(unsigned int divider);
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void (*set_backlight_mode)(unsigned int mode);
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/* ///////////////////////// */
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int (*adjust_fps)(void *cmdq, int fps, struct LCM_PARAMS *params);
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void (*validate_roi)(int *x, int *y, int *width, int *height);
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void (*scale)(void *handle, enum LCM_SCALE_TYPE scale);
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void (*setroi)(int x, int y, int width, int height, void *handle);
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/* ///////////ESD_RECOVERY////////////////////// */
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unsigned int (*esd_check)(void);
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unsigned int (*esd_recover)(void);
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unsigned int (*check_status)(void);
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unsigned int (*ata_check)(unsigned char *buffer);
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void (*read_fb)(unsigned char *buffer);
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int (*ioctl)(enum LCM_DRV_IOCTL_CMD cmd, unsigned int data);
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/* /////////////////////////////////////////////// */
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void (*enter_idle)(void);
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void (*exit_idle)(void);
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void (*change_fps)(unsigned int mode);
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/* //switch mode */
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void *(*switch_mode)(int mode);
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void (*set_cmd)(void *handle, int *mode, unsigned int cmd_num);
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void (*set_lcm_cmd)(void *handle, unsigned int *lcm_cmd,
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unsigned int *lcm_count, unsigned int *lcm_value);
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/* /////////////PWM///////////////////////////// */
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void (*set_pwm_for_mix)(int enable);
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void (*aod)(int enter);
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/* /////////////DynFPS///////////////////////////// */
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void (*dfps_send_lcm_cmd)(void *cmdq_handle,
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unsigned int from_level, unsigned int to_level, struct LCM_PARAMS *params);
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bool (*dfps_need_send_cmd)(
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unsigned int from_level, unsigned int to_level, struct LCM_PARAMS *params);
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};
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/* LCM Driver Functions */
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/* ------------------------------------------------------------------------- */
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const struct LCM_DRIVER *LCM_GetDriver(void);
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unsigned char which_lcd_module_triple(void);
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int lcm_vgp_supply_enable(void);
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int lcm_vgp_supply_disable(void);
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extern enum LCM_DSI_MODE_CON lcm_dsi_mode;
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extern int display_bias_enable(void);
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extern int display_bias_disable(void);
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extern int display_bias_regulator_init(void);
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#endif /* __LCM_DRV_H__ */
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