352 lines
14 KiB
C
352 lines
14 KiB
C
/*
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* FarSync X21 driver for Linux
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*
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* Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
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*
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* Copyright (C) 2001 FarSite Communications Ltd.
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* www.farsite.co.uk
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
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*
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* For the most part this file only contains structures and information
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* that is visible to applications outside the driver. Shared memory
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* layout etc is internal to the driver and described within farsync.c.
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* Overlap exists in that the values used for some fields within the
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* ioctl interface extend into the cards firmware interface so values in
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* this file may not be changed arbitrarily.
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*/
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/* What's in a name
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*
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* The project name for this driver is Oscar. The driver is intended to be
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* used with the FarSite T-Series cards (T2P & T4P) running in the high
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* speed frame shifter mode. This is sometimes referred to as X.21 mode
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* which is a complete misnomer as the card continues to support V.24 and
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* V.35 as well as X.21.
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*
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* A short common prefix is useful for routines within the driver to avoid
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* conflict with other similar drivers and I chosen to use "fst_" for this
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* purpose (FarSite T-series).
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*
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* Finally the device driver needs a short network interface name. Since
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* "hdlc" is already in use I've chosen the even less informative "sync"
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* for the present.
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*/
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#define FST_NAME "fst" /* In debug/info etc */
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#define FST_NDEV_NAME "sync" /* For net interface */
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#define FST_DEV_NAME "farsync" /* For misc interfaces */
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/* User version number
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*
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* This version number is incremented with each official release of the
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* package and is a simplified number for normal user reference.
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* Individual files are tracked by the version control system and may
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* have individual versions (or IDs) that move much faster than the
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* the release version as individual updates are tracked.
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*/
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#define FST_USER_VERSION "1.04"
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/* Ioctl call command values
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*/
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#define FSTWRITE (SIOCDEVPRIVATE+10)
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#define FSTCPURESET (SIOCDEVPRIVATE+11)
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#define FSTCPURELEASE (SIOCDEVPRIVATE+12)
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#define FSTGETCONF (SIOCDEVPRIVATE+13)
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#define FSTSETCONF (SIOCDEVPRIVATE+14)
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/* FSTWRITE
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*
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* Used to write a block of data (firmware etc) before the card is running
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*/
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struct fstioc_write {
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unsigned int size;
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unsigned int offset;
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unsigned char data[0];
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};
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/* FSTCPURESET and FSTCPURELEASE
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*
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* These take no additional data.
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* FSTCPURESET forces the cards CPU into a reset state and holds it there.
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* FSTCPURELEASE releases the CPU from this reset state allowing it to run,
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* the reset vector should be setup before this ioctl is run.
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*/
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/* FSTGETCONF and FSTSETCONF
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*
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* Get and set a card/ports configuration.
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* In order to allow selective setting of items and for the kernel to
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* indicate a partial status response the first field "valid" is a bitmask
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* indicating which other fields in the structure are valid.
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* Many of the field names in this structure match those used in the
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* firmware shared memory configuration interface and come originally from
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* the NT header file Smc.h
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*
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* When used with FSTGETCONF this structure should be zeroed before use.
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* This is to allow for possible future expansion when some of the fields
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* might be used to indicate a different (expanded) structure.
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*/
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struct fstioc_info {
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unsigned int valid; /* Bits of structure that are valid */
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unsigned int nports; /* Number of serial ports */
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unsigned int type; /* Type index of card */
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unsigned int state; /* State of card */
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unsigned int index; /* Index of port ioctl was issued on */
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unsigned int smcFirmwareVersion;
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unsigned long kernelVersion; /* What Kernel version we are working with */
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unsigned short lineInterface; /* Physical interface type */
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unsigned char proto; /* Line protocol */
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unsigned char internalClock; /* 1 => internal clock, 0 => external */
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unsigned int lineSpeed; /* Speed in bps */
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unsigned int v24IpSts; /* V.24 control input status */
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unsigned int v24OpSts; /* V.24 control output status */
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unsigned short clockStatus; /* lsb: 0=> present, 1=> absent */
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unsigned short cableStatus; /* lsb: 0=> present, 1=> absent */
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unsigned short cardMode; /* lsb: LED id mode */
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unsigned short debug; /* Debug flags */
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unsigned char transparentMode; /* Not used always 0 */
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unsigned char invertClock; /* Invert clock feature for syncing */
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unsigned char startingSlot; /* Time slot to use for start of tx */
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unsigned char clockSource; /* External or internal */
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unsigned char framing; /* E1, T1 or J1 */
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unsigned char structure; /* unframed, double, crc4, f4, f12, */
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/* f24 f72 */
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unsigned char interface; /* rj48c or bnc */
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unsigned char coding; /* hdb3 b8zs */
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unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
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unsigned char equalizer; /* short or lon haul settings */
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unsigned char loopMode; /* various loopbacks */
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unsigned char range; /* cable lengths */
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unsigned char txBufferMode; /* tx elastic buffer depth */
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unsigned char rxBufferMode; /* rx elastic buffer depth */
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unsigned char losThreshold; /* Attenuation on LOS signal */
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unsigned char idleCode; /* Value to send as idle timeslot */
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unsigned int receiveBufferDelay; /* delay thro rx buffer timeslots */
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unsigned int framingErrorCount; /* framing errors */
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unsigned int codeViolationCount; /* code violations */
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unsigned int crcErrorCount; /* CRC errors */
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int lineAttenuation; /* in dB*/
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unsigned short lossOfSignal;
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unsigned short receiveRemoteAlarm;
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unsigned short alarmIndicationSignal;
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};
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/* "valid" bitmask */
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#define FSTVAL_NONE 0x00000000 /* Nothing valid (firmware not running).
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* Slight misnomer. In fact nports,
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* type, state and index will be set
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* based on hardware detected.
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*/
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#define FSTVAL_OMODEM 0x0000001F /* First 5 bits correspond to the
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* output status bits defined for
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* v24OpSts
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*/
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#define FSTVAL_SPEED 0x00000020 /* internalClock, lineSpeed, clockStatus
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*/
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#define FSTVAL_CABLE 0x00000040 /* lineInterface, cableStatus */
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#define FSTVAL_IMODEM 0x00000080 /* v24IpSts */
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#define FSTVAL_CARD 0x00000100 /* nports, type, state, index,
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* smcFirmwareVersion
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*/
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#define FSTVAL_PROTO 0x00000200 /* proto */
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#define FSTVAL_MODE 0x00000400 /* cardMode */
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#define FSTVAL_PHASE 0x00000800 /* Clock phase */
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#define FSTVAL_TE1 0x00001000 /* T1E1 Configuration */
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#define FSTVAL_DEBUG 0x80000000 /* debug */
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#define FSTVAL_ALL 0x00001FFF /* Note: does not include DEBUG flag */
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/* "type" */
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#define FST_TYPE_NONE 0 /* Probably should never happen */
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#define FST_TYPE_T2P 1 /* T2P X21 2 port card */
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#define FST_TYPE_T4P 2 /* T4P X21 4 port card */
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#define FST_TYPE_T1U 3 /* T1U X21 1 port card */
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#define FST_TYPE_T2U 4 /* T2U X21 2 port card */
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#define FST_TYPE_T4U 5 /* T4U X21 4 port card */
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#define FST_TYPE_TE1 6 /* T1E1 X21 1 port card */
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/* "family" */
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#define FST_FAMILY_TXP 0 /* T2P or T4P */
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#define FST_FAMILY_TXU 1 /* T1U or T2U or T4U */
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/* "state" */
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#define FST_UNINIT 0 /* Raw uninitialised state following
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* system startup */
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#define FST_RESET 1 /* Processor held in reset state */
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#define FST_DOWNLOAD 2 /* Card being downloaded */
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#define FST_STARTING 3 /* Released following download */
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#define FST_RUNNING 4 /* Processor running */
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#define FST_BADVERSION 5 /* Bad shared memory version detected */
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#define FST_HALTED 6 /* Processor flagged a halt */
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#define FST_IFAILED 7 /* Firmware issued initialisation failed
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* interrupt
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*/
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/* "lineInterface" */
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#define V24 1
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#define X21 2
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#define V35 3
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#define X21D 4
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#define T1 5
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#define E1 6
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#define J1 7
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/* "proto" */
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#define FST_RAW 4 /* Two way raw packets */
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#define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */
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/* "internalClock" */
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#define INTCLK 1
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#define EXTCLK 0
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/* "v24IpSts" bitmask */
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#define IPSTS_CTS 0x00000001 /* Clear To Send (Indicate for X.21) */
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#define IPSTS_INDICATE IPSTS_CTS
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#define IPSTS_DSR 0x00000002 /* Data Set Ready (T2P Port A) */
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#define IPSTS_DCD 0x00000004 /* Data Carrier Detect */
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#define IPSTS_RI 0x00000008 /* Ring Indicator (T2P Port A) */
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#define IPSTS_TMI 0x00000010 /* Test Mode Indicator (Not Supported)*/
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/* "v24OpSts" bitmask */
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#define OPSTS_RTS 0x00000001 /* Request To Send (Control for X.21) */
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#define OPSTS_CONTROL OPSTS_RTS
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#define OPSTS_DTR 0x00000002 /* Data Terminal Ready */
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#define OPSTS_DSRS 0x00000004 /* Data Signalling Rate Select (Not
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* Supported) */
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#define OPSTS_SS 0x00000008 /* Select Standby (Not Supported) */
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#define OPSTS_LL 0x00000010 /* Maintenance Test (Not Supported) */
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/* "cardMode" bitmask */
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#define CARD_MODE_IDENTIFY 0x0001
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/*
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* Constants for T1/E1 configuration
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*/
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/*
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* Clock source
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*/
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#define CLOCKING_SLAVE 0
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#define CLOCKING_MASTER 1
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/*
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* Framing
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*/
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#define FRAMING_E1 0
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#define FRAMING_J1 1
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#define FRAMING_T1 2
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/*
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* Structure
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*/
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#define STRUCTURE_UNFRAMED 0
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#define STRUCTURE_E1_DOUBLE 1
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#define STRUCTURE_E1_CRC4 2
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#define STRUCTURE_E1_CRC4M 3
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#define STRUCTURE_T1_4 4
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#define STRUCTURE_T1_12 5
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#define STRUCTURE_T1_24 6
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#define STRUCTURE_T1_72 7
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/*
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* Interface
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*/
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#define INTERFACE_RJ48C 0
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#define INTERFACE_BNC 1
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/*
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* Coding
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*/
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#define CODING_HDB3 0
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#define CODING_NRZ 1
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#define CODING_CMI 2
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#define CODING_CMI_HDB3 3
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#define CODING_CMI_B8ZS 4
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#define CODING_AMI 5
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#define CODING_AMI_ZCS 6
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#define CODING_B8ZS 7
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/*
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* Line Build Out
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*/
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#define LBO_0dB 0
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#define LBO_7dB5 1
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#define LBO_15dB 2
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#define LBO_22dB5 3
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/*
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* Range for long haul t1 > 655ft
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*/
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#define RANGE_0_133_FT 0
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#define RANGE_0_40_M RANGE_0_133_FT
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#define RANGE_133_266_FT 1
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#define RANGE_40_81_M RANGE_133_266_FT
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#define RANGE_266_399_FT 2
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#define RANGE_81_122_M RANGE_266_399_FT
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#define RANGE_399_533_FT 3
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#define RANGE_122_162_M RANGE_399_533_FT
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#define RANGE_533_655_FT 4
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#define RANGE_162_200_M RANGE_533_655_FT
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/*
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* Receive Equaliser
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*/
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#define EQUALIZER_SHORT 0
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#define EQUALIZER_LONG 1
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/*
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* Loop modes
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*/
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#define LOOP_NONE 0
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#define LOOP_LOCAL 1
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#define LOOP_PAYLOAD_EXC_TS0 2
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#define LOOP_PAYLOAD_INC_TS0 3
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#define LOOP_REMOTE 4
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/*
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* Buffer modes
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*/
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#define BUFFER_2_FRAME 0
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#define BUFFER_1_FRAME 1
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#define BUFFER_96_BIT 2
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#define BUFFER_NONE 3
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/* Debug support
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*
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* These should only be enabled for development kernels, production code
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* should define FST_DEBUG=0 in order to exclude the code.
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* Setting FST_DEBUG=1 will include all the debug code but in a disabled
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* state, use the FSTSETCONF ioctl to enable specific debug actions, or
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* FST_DEBUG can be set to prime the debug selection.
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*/
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#define FST_DEBUG 0x0000
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#if FST_DEBUG
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extern int fst_debug_mask; /* Bit mask of actions to debug, bits
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* listed below. Note: Bit 0 is used
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* to trigger the inclusion of this
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* code, without enabling any actions.
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*/
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#define DBG_INIT 0x0002 /* Card detection and initialisation */
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#define DBG_OPEN 0x0004 /* Open and close sequences */
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#define DBG_PCI 0x0008 /* PCI config operations */
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#define DBG_IOCTL 0x0010 /* Ioctls and other config */
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#define DBG_INTR 0x0020 /* Interrupt routines (be careful) */
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#define DBG_TX 0x0040 /* Packet transmission */
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#define DBG_RX 0x0080 /* Packet reception */
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#define DBG_CMD 0x0100 /* Port command issuing */
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#define DBG_ASS 0xFFFF /* Assert like statements. Code that
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* should never be reached, if you see
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* one of these then I've been an ass
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*/
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#endif /* FST_DEBUG */
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