288 lines
7 KiB
C
288 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R8A66597 UDC
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*
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* Copyright (C) 2007-2009 Renesas Solutions Corp.
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*
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* Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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*/
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#ifndef __R8A66597_H__
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#define __R8A66597_H__
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#include <linux/clk.h>
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#include <linux/usb/r8a66597.h>
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#define R8A66597_MAX_SAMPLING 10
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#define R8A66597_MAX_NUM_PIPE 8
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#define R8A66597_MAX_NUM_BULK 3
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#define R8A66597_MAX_NUM_ISOC 2
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#define R8A66597_MAX_NUM_INT 2
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#define R8A66597_BASE_PIPENUM_BULK 3
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#define R8A66597_BASE_PIPENUM_ISOC 1
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#define R8A66597_BASE_PIPENUM_INT 6
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#define R8A66597_BASE_BUFNUM 6
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#define R8A66597_MAX_BUFNUM 0x4F
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#define is_bulk_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
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(pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
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#define is_interrupt_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
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(pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
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#define is_isoc_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
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(pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
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#define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
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struct r8a66597_pipe_info {
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u16 pipe;
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u16 epnum;
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u16 maxpacket;
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u16 type;
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u16 interval;
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u16 dir_in;
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};
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struct r8a66597_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct r8a66597_ep {
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struct usb_ep ep;
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struct r8a66597 *r8a66597;
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struct r8a66597_dma *dma;
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struct list_head queue;
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unsigned busy:1;
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unsigned wedge:1;
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unsigned internal_ccpl:1; /* use only control */
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/* this member can able to after r8a66597_enable */
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unsigned use_dma:1;
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u16 pipenum;
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u16 type;
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/* register address */
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unsigned char fifoaddr;
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unsigned char fifosel;
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unsigned char fifoctr;
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unsigned char pipectr;
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unsigned char pipetre;
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unsigned char pipetrn;
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};
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struct r8a66597_dma {
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unsigned used:1;
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unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
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};
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struct r8a66597 {
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spinlock_t lock;
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void __iomem *reg;
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void __iomem *sudmac_reg;
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struct clk *clk;
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struct r8a66597_platdata *pdata;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
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struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
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struct r8a66597_ep *epaddr2ep[16];
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struct r8a66597_dma dma;
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struct timer_list timer;
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struct usb_request *ep0_req; /* for internal request */
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u16 ep0_data; /* for internal request */
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u16 old_vbus;
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u16 scount;
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u16 old_dvsq;
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u16 device_status; /* for GET_STATUS */
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/* pipe config */
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unsigned char bulk;
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unsigned char interrupt;
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unsigned char isochronous;
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unsigned char num_dma;
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unsigned irq_sense_low:1;
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};
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#define gadget_to_r8a66597(_gadget) \
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container_of(_gadget, struct r8a66597, gadget)
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#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
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#define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
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static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
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{
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return ioread16(r8a66597->reg + offset);
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}
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static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
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unsigned long offset,
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unsigned char *buf,
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int len)
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{
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void __iomem *fifoaddr = r8a66597->reg + offset;
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unsigned int data = 0;
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int i;
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if (r8a66597->pdata->on_chip) {
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/* 32-bit accesses for on_chip controllers */
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/* aligned buf case */
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if (len >= 4 && !((unsigned long)buf & 0x03)) {
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ioread32_rep(fifoaddr, buf, len / 4);
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buf += len & ~0x03;
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len &= 0x03;
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}
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/* unaligned buf case */
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for (i = 0; i < len; i++) {
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if (!(i & 0x03))
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data = ioread32(fifoaddr);
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buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
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}
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} else {
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/* 16-bit accesses for external controllers */
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/* aligned buf case */
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if (len >= 2 && !((unsigned long)buf & 0x01)) {
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ioread16_rep(fifoaddr, buf, len / 2);
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buf += len & ~0x01;
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len &= 0x01;
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}
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/* unaligned buf case */
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for (i = 0; i < len; i++) {
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if (!(i & 0x01))
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data = ioread16(fifoaddr);
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buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
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}
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}
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}
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static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
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unsigned long offset)
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{
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iowrite16(val, r8a66597->reg + offset);
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}
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static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
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u16 val, u16 pat, unsigned long offset)
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{
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u16 tmp;
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tmp = r8a66597_read(r8a66597, offset);
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tmp = tmp & (~pat);
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tmp = tmp | val;
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r8a66597_write(r8a66597, tmp, offset);
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}
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#define r8a66597_bclr(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, 0, val, offset)
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#define r8a66597_bset(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, val, 0, offset)
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static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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struct r8a66597_ep *ep,
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unsigned char *buf,
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int len)
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{
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void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
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int adj = 0;
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int i;
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if (r8a66597->pdata->on_chip) {
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/* 32-bit access only if buf is 32-bit aligned */
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if (len >= 4 && !((unsigned long)buf & 0x03)) {
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iowrite32_rep(fifoaddr, buf, len / 4);
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buf += len & ~0x03;
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len &= 0x03;
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}
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} else {
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/* 16-bit access only if buf is 16-bit aligned */
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if (len >= 2 && !((unsigned long)buf & 0x01)) {
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iowrite16_rep(fifoaddr, buf, len / 2);
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buf += len & ~0x01;
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len &= 0x01;
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}
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}
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/* adjust fifo address in the little endian case */
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if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
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if (r8a66597->pdata->on_chip)
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adj = 0x03; /* 32-bit wide */
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else
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adj = 0x01; /* 16-bit wide */
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}
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if (r8a66597->pdata->wr0_shorted_to_wr1)
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r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
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for (i = 0; i < len; i++)
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iowrite8(buf[i], fifoaddr + adj - (i & adj));
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if (r8a66597->pdata->wr0_shorted_to_wr1)
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r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
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}
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static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
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{
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u16 clock = 0;
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switch (pdata->xtal) {
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case R8A66597_PLATDATA_XTAL_12MHZ:
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clock = XTAL12;
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break;
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case R8A66597_PLATDATA_XTAL_24MHZ:
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clock = XTAL24;
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break;
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case R8A66597_PLATDATA_XTAL_48MHZ:
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clock = XTAL48;
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break;
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default:
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printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
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break;
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}
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return clock;
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}
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static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
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unsigned long offset)
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{
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return ioread32(r8a66597->sudmac_reg + offset);
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}
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static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
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unsigned long offset)
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{
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iowrite32(val, r8a66597->sudmac_reg + offset);
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}
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#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
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#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
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#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
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#define enable_irq_ready(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define disable_irq_ready(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define enable_irq_empty(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define disable_irq_empty(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define enable_irq_nrdy(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#define disable_irq_nrdy(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#endif /* __R8A66597_H__ */
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