112 lines
4 KiB
C
112 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Argus Lin <argus.lin@mediatek.com>
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*/
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#ifndef __PMIF_H__
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#define __PMIF_H__
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#include <linux/clk.h>
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enum {
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SPMI_MASTER_0 = 0,
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SPMI_MASTER_1,
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SPMI_MASTER_2,
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SPMI_MASTER_3
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};
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/**
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* @base: pmif base address.
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* @regs: pmif register offset table.
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* @spmimst_base: spmi master base address.
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* @spmimst_regs: spmi master register offset table.
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* @infra_base: infra base address.
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* @infra_regs: infra register offset table.
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* @topckgen_base: topckgen base address.
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* @topckgen_regs: topckgen register offset table.
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* @toprgu_base: toprgu base address.
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* @toprgu_regs: toprgu register offset table.
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* @dbgregs: pmif debug register offset table.
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* @dbgver: pmif debug version.
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* @swinf_ch_start: indicate sw channel start number, lower is hw channel.
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* @ap_swinf_no: indicate ap sw channel number.
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* @write: indicate write cmd.
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* @mstid: indicate mstid.
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* @pmifid: indicate pmifid.
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* @irq: indicate irq number.
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* @grpid: indicates which group id we used.
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* @lock: indicate lock key.
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* @pmifThread_lock: indicate pmif interrupt thread pm protection.
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* @pmif_mutex: indicate pmif interrupt thread mutex protection.
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* @spmic: indicate spmi controller.
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* @pmif_sys_ck: indicate pmif infracfg_ao sys_ck cg.
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* @pmif_tmr_ck: indicate pmif infracfg_ao tmr_ck cg.
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* @pmif_clk_mux: indicate pmif clock source, be as consumer.
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* @pmif_clk_osc_d10: indicate pmif clock source to osc d10.
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* @pmif_clk26m: indicate pmif clock source to clk26m.
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* @spmimst_clk_mux: indicate spmimst clock source, be as consumer.
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* @spmimst_clk26m: indicate spmimst clock sourc to clk26m.
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* @spmimst_clk_osc_d10: indicate spmimst clock source to osc d10.
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* @cmd: sends a non-data command sequence on the SPMI bus.
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* @read_cmd: sends a register read command sequence on the SPMI bus.
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* @write_cmd: sends a register write command sequence on the SPMI bus.
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* @pmif_enable_clk_set: pmif clock set.
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* @pmif_force_normal_mode: enable pmif normal mode.
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* @pmif_enable_swinf: enable sw interface arbritation.
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* @pmif_enable_cmdIssue: enable cmd enable to access.
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* @pmif_enable: set pmif all done.
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* @is_pmif_init_done: check if pmif init done.
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* @pmif_enable_reset: SW reset pmif.
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* @pmif_cali_clock: calibrate spmi master clock.
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* @spmi_config_master: config spmi master.
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*/
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struct pmif {
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void __iomem *base;
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const u32 *regs;
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void __iomem *spmimst_base;
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const u32 *spmimst_regs;
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void __iomem *infra_base;
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const u32 *infra_regs;
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void __iomem *topckgen_base;
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const u32 *topckgen_regs;
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void __iomem *toprgu_base;
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const u32 *toprgu_regs;
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const u32 *dbgregs;
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u32 dbgver;
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u32 swinf_ch_start;
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u32 ap_swinf_no;
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int write;
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int mstid;
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int pmifid;
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int irq;
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int grpid;
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raw_spinlock_t lock;
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struct wakeup_source *pmifThread_lock;
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struct mutex pmif_mutex;
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struct spmi_controller *spmic;
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struct clk *pmif_sys_ck;
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struct clk *pmif_tmr_ck;
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struct clk *pmif_clk_mux;
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struct clk *pmif_clk_osc_d10;
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struct clk *pmif_clk26m;
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struct clk *spmimst_clk_mux;
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struct clk *spmimst_clk26m;
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struct clk *spmimst_clk_osc_d10;
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int (*cmd)(struct spmi_controller *ctrl, unsigned int opcode);
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int (*read_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u16 addr, u8 *buf, size_t len);
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int (*write_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u16 addr, const u8 *buf, size_t len);
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void (*pmif_enable_clk_set)(struct pmif *arb);
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void (*pmif_force_normal_mode)(struct pmif *arb);
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void (*pmif_enable_swinf)(struct pmif *arb, unsigned int chan_no,
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unsigned int swinf_no);
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void (*pmif_enable_cmdIssue)(struct pmif *arb, bool en);
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void (*pmif_enable)(struct pmif *arb);
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int (*is_pmif_init_done)(struct pmif *arb);
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void (*pmif_enable_reset)(struct pmif *arb);
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int (*pmif_cali_clock)(struct pmif *arb);
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int (*spmi_config_master)(struct pmif *arb, unsigned int mstid,
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bool en);
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};
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#endif /*__PMIF_H__*/
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