275 lines
7.1 KiB
C
275 lines
7.1 KiB
C
/*
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* Atmel AT91 AIC (Advanced Interrupt Controller) driver
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irq-atmel-aic-common.h"
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/* Number of irq lines managed by AIC */
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#define NR_AIC_IRQS 32
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#define AT91_AIC_SMR(n) ((n) * 4)
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#define AT91_AIC_SVR(n) (0x80 + ((n) * 4))
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#define AT91_AIC_IVR 0x100
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#define AT91_AIC_FVR 0x104
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#define AT91_AIC_ISR 0x108
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#define AT91_AIC_IPR 0x10c
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#define AT91_AIC_IMR 0x110
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#define AT91_AIC_CISR 0x114
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#define AT91_AIC_IECR 0x120
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#define AT91_AIC_IDCR 0x124
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#define AT91_AIC_ICCR 0x128
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#define AT91_AIC_ISCR 0x12c
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#define AT91_AIC_EOICR 0x130
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#define AT91_AIC_SPU 0x134
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#define AT91_AIC_DCR 0x138
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static struct irq_domain *aic_domain;
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static asmlinkage void __exception_irq_entry
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aic_handle(struct pt_regs *regs)
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{
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struct irq_domain_chip_generic *dgc = aic_domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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u32 irqnr;
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u32 irqstat;
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irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
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irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
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if (!irqstat)
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irq_reg_writel(gc, 0, AT91_AIC_EOICR);
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else
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handle_domain_irq(aic_domain, irqnr, regs);
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}
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static int aic_retrigger(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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/* Enable interrupt on AIC5 */
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irq_gc_lock(gc);
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irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
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irq_gc_unlock(gc);
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return 0;
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}
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static int aic_set_type(struct irq_data *d, unsigned type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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unsigned int smr;
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int ret;
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smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
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ret = aic_common_set_type(d, type, &smr);
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if (ret)
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return ret;
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irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
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return 0;
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}
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#ifdef CONFIG_PM
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static void aic_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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irq_gc_lock(gc);
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irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
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irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
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irq_gc_unlock(gc);
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}
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static void aic_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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irq_gc_lock(gc);
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irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
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irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
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irq_gc_unlock(gc);
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}
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static void aic_pm_shutdown(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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irq_gc_lock(gc);
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irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
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irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
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irq_gc_unlock(gc);
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}
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#else
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#define aic_suspend NULL
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#define aic_resume NULL
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#define aic_pm_shutdown NULL
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#endif /* CONFIG_PM */
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static void __init aic_hw_init(struct irq_domain *domain)
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{
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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irq_reg_writel(gc, 0, AT91_AIC_EOICR);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
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/* No debugging in AIC: Debug (Protect) Control Register */
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irq_reg_writel(gc, 0, AT91_AIC_DCR);
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/* Disable and clear all interrupts initially */
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irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
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irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
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for (i = 0; i < 32; i++)
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irq_reg_writel(gc, i, AT91_AIC_SVR(i));
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}
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static int aic_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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struct irq_domain_chip_generic *dgc = d->gc;
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struct irq_chip_generic *gc;
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unsigned long flags;
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unsigned smr;
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int idx;
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int ret;
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if (!dgc)
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return -EINVAL;
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ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
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out_hwirq, out_type);
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if (ret)
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return ret;
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idx = intspec[0] / dgc->irqs_per_chip;
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if (idx >= dgc->num_chips)
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return -EINVAL;
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gc = dgc->gc[idx];
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irq_gc_lock_irqsave(gc, flags);
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smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
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aic_common_set_priority(intspec[2], &smr);
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irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
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irq_gc_unlock_irqrestore(gc, flags);
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return ret;
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}
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static const struct irq_domain_ops aic_irq_ops = {
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.map = irq_map_generic_chip,
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.xlate = aic_irq_domain_xlate,
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};
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static void __init at91rm9200_aic_irq_fixup(void)
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{
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aic_common_rtc_irq_fixup();
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}
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static void __init at91sam9260_aic_irq_fixup(void)
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{
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aic_common_rtt_irq_fixup();
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}
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static void __init at91sam9g45_aic_irq_fixup(void)
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{
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aic_common_rtc_irq_fixup();
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aic_common_rtt_irq_fixup();
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}
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static const struct of_device_id aic_irq_fixups[] __initconst = {
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{ .compatible = "atmel,at91rm9200", .data = at91rm9200_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9g45", .data = at91sam9g45_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9n12", .data = at91rm9200_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9rl", .data = at91sam9g45_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9x5", .data = at91rm9200_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9260", .data = at91sam9260_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9261", .data = at91sam9260_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9263", .data = at91sam9260_aic_irq_fixup },
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{ .compatible = "atmel,at91sam9g20", .data = at91sam9260_aic_irq_fixup },
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{ /* sentinel */ },
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};
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static int __init aic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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if (aic_domain)
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return -EEXIST;
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domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
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NR_AIC_IRQS, aic_irq_fixups);
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if (IS_ERR(domain))
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return PTR_ERR(domain);
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aic_domain = domain;
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
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gc->chip_types[0].regs.enable = AT91_AIC_IECR;
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gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
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gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
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gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
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gc->chip_types[0].chip.irq_set_type = aic_set_type;
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gc->chip_types[0].chip.irq_suspend = aic_suspend;
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gc->chip_types[0].chip.irq_resume = aic_resume;
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gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
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aic_hw_init(domain);
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set_handle_irq(aic_handle);
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return 0;
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}
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IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);
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