177 lines
5.9 KiB
C
177 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __EDMA3_REG_H__
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#define __EDMA3_REG_H__
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#include <linux/kernel.h>
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#include <linux/io.h>
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#define EDMA30_REG_SHOW_RANGE 0x200
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/* APU_EDMA2_CFG_0 */
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#define EXT_IOMMU_READ BIT(29)
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#define EXT_IOMMU_WRITE BIT(31)
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#define EXT_CMDQ_INT_ENABLE BIT(28)
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#define APU_EDMA3_VERSION 0x000
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#define APU_EDMA3_CTRL 0x004
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#define APU_EDMA3_STATE 0x008
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#define APU_EDMA3_ERR_STATUS 0x00C
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#define APU_EDMA3_ERR_MASK 0x010
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#define APU_EDMA3_ERR_DES_ID 0x014
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#define APU_EDMA3_ERR_CH_INDEX 0x018
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#define APU_EDMA3_DONE_STATUS 0x01C
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#define APU_EDMA3_DONE_MASK 0x020
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#define APU_EDMA3_HW_SYNC_A 0x024
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#define APU_EDMA3_HW_SYNC_B 0x028
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#define APU_EDMA3_PMU_CTRL 0x02C
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#define APU_EDMA3_PMU_STATE 0x030
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#define APU_EDMA3_UFBC_CTRL 0x080
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#define APU_EDMA3_UFBC_GROUP_CTRL 0x084
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#define APU_EDMA3_UFBC_DBG_STATE 0x088
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#define APU_EDMA3_UFBC_MON_GMC 0x08C
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#define APU_EDMA3_UFBC_CHECK_SUM 0x090
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#define APU_EDMA3_UFBDC_CTRL 0x0C0
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#define APU_EDMA3_UFBDC_GROUP_CTRL 0x0C4
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#define APU_EDMA3_UFBDC_DBG_STATE 0x0C8
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#define APU_EDMA3_UFBDC_MON_GMC 0x0CC
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#define APU_EDMA3_UFBDC_VERSION_A 0x0D0
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#define APU_EDMA3_UFBDC_VERSION_B 0x0D4
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#define APU_EDMA3_UFBDC_VERSION_C 0x0D8
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#define APU_EDMA3_UFBDC_VERSION_D 0x0DC
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#define APU_EDMA3_CMDQ_CH0_LO_A 0x800
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#define APU_EDMA3_CMDQ_CH0_LO_B 0x804
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#define APU_EDMA3_CMDQ_CH0_LO_C 0x808
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#define APU_EDMA3_CMDQ_CH0_LO_D 0x80C
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#define APU_EDMA3_CMDQ_CH0_LO_E 0x810
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#define APU_EDMA3_CMDQ_CH0_LO_F 0x814
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#define APU_EDMA3_CMDQ_CH0_HI_A 0x880
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#define APU_EDMA3_CMDQ_CH0_HI_B 0x884
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#define APU_EDMA3_CMDQ_CH0_HI_C 0x888
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#define APU_EDMA3_CMDQ_CH0_HI_D 0x88C
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#define APU_EDMA3_CMDQ_CH0_HI_E 0x890
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#define APU_EDMA3_CMDQ_CH0_HI_F 0x894
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#define APU_EDMA3_CMDQ_CH1_LO_A 0x900
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#define APU_EDMA3_CMDQ_CH1_LO_B 0x904
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#define APU_EDMA3_CMDQ_CH1_LO_C 0x908
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#define APU_EDMA3_CMDQ_CH1_LO_D 0x90C
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#define APU_EDMA3_CMDQ_CH1_LO_E 0x910
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#define APU_EDMA3_CMDQ_CH1_LO_F 0x914
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#define APU_EDMA3_CMDQ_CH1_HI_A 0x980
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#define APU_EDMA3_CMDQ_CH1_HI_B 0x984
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#define APU_EDMA3_CMDQ_CH1_HI_C 0x988
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#define APU_EDMA3_CMDQ_CH1_HI_D 0x98C
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#define APU_EDMA3_CMDQ_CH1_HI_E 0x990
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#define APU_EDMA3_CMDQ_CH1_HI_F 0x994
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#define APU_EDMA3_CMDQ_CH2_LO_A 0xA00
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#define APU_EDMA3_CMDQ_CH2_LO_B 0xA04
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#define APU_EDMA3_CMDQ_CH2_LO_C 0xA08
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#define APU_EDMA3_CMDQ_CH2_LO_D 0xA0C
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#define APU_EDMA3_CMDQ_CH2_LO_E 0xA10
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#define APU_EDMA3_CMDQ_CH2_LO_F 0xA14
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#define APU_EDMA3_CMDQ_CH2_HI_A 0xA80
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#define APU_EDMA3_CMDQ_CH2_HI_B 0xA84
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#define APU_EDMA3_CMDQ_CH2_HI_C 0xA88
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#define APU_EDMA3_CMDQ_CH2_HI_D 0xA8C
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#define APU_EDMA3_CMDQ_CH2_HI_E 0xA90
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#define APU_EDMA3_CMDQ_CH2_HI_F 0xA94
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#define APU_EDMA3_CMDQ_CH3_LO_A 0xB00
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#define APU_EDMA3_CMDQ_CH3_LO_B 0xB04
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#define APU_EDMA3_CMDQ_CH3_LO_C 0xB08
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#define APU_EDMA3_CMDQ_CH3_LO_D 0xB0C
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#define APU_EDMA3_CMDQ_CH3_LO_E 0xB10
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#define APU_EDMA3_CMDQ_CH3_LO_F 0xB14
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#define APU_EDMA3_CMDQ_CH3_HI_A 0xB80
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#define APU_EDMA3_CMDQ_CH3_HI_B 0xB84
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#define APU_EDMA3_CMDQ_CH3_HI_C 0xB88
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#define APU_EDMA3_CMDQ_CH3_HI_D 0xB8C
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#define APU_EDMA3_CMDQ_CH3_HI_E 0xB90
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#define APU_EDMA3_CMDQ_CH3_HI_F 0xB94
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#define APU_EDMA3_CMDQ_CH4_LO_A 0xC00
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#define APU_EDMA3_CMDQ_CH4_LO_B 0xC04
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#define APU_EDMA3_CMDQ_CH4_LO_C 0xC08
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#define APU_EDMA3_CMDQ_CH4_LO_D 0xC0C
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#define APU_EDMA3_CMDQ_CH4_LO_E 0xC10
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#define APU_EDMA3_CMDQ_CH4_LO_F 0xC14
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#define APU_EDMA3_CMDQ_CH4_HI_A 0xC80
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#define APU_EDMA3_CMDQ_CH4_HI_B 0xC84
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#define APU_EDMA3_CMDQ_CH4_HI_C 0xC88
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#define APU_EDMA3_CMDQ_CH4_HI_D 0xC8C
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#define APU_EDMA3_CMDQ_CH4_HI_E 0xC90
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#define APU_EDMA3_CMDQ_CH4_HI_F 0xC94
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#define APU_EDMA3_CMDQ_CH5_LO_A 0xD00
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#define APU_EDMA3_CMDQ_CH5_LO_B 0xD04
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#define APU_EDMA3_CMDQ_CH5_LO_C 0xD08
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#define APU_EDMA3_CMDQ_CH5_LO_D 0xD0C
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#define APU_EDMA3_CMDQ_CH5_LO_E 0xD10
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#define APU_EDMA3_CMDQ_CH5_LO_F 0xD14
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#define APU_EDMA3_CMDQ_CH5_HI_A 0xD80
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#define APU_EDMA3_CMDQ_CH5_HI_B 0xD84
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#define APU_EDMA3_CMDQ_CH5_HI_C 0xD88
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#define APU_EDMA3_CMDQ_CH5_HI_D 0xD8C
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#define APU_EDMA3_CMDQ_CH5_HI_E 0xD90
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#define APU_EDMA3_CMDQ_CH5_HI_F 0xD94
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#define APU_EDMA3_CMDQ_CH6_LO_A 0xE00
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#define APU_EDMA3_CMDQ_CH6_LO_B 0xE04
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#define APU_EDMA3_CMDQ_CH6_LO_C 0xE08
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#define APU_EDMA3_CMDQ_CH6_LO_D 0xE0C
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#define APU_EDMA3_CMDQ_CH6_LO_E 0xE10
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#define APU_EDMA3_CMDQ_CH6_LO_F 0xE14
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#define APU_EDMA3_CMDQ_CH6_HI_A 0xE80
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#define APU_EDMA3_CMDQ_CH6_HI_B 0xE84
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#define APU_EDMA3_CMDQ_CH6_HI_C 0xE88
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#define APU_EDMA3_CMDQ_CH6_HI_D 0xE8C
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#define APU_EDMA3_CMDQ_CH6_HI_E 0xE90
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#define APU_EDMA3_CMDQ_CH6_HI_F 0xE94
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#define APU_EDMA3_CMDQ_CH7_LO_A 0xF00
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#define APU_EDMA3_CMDQ_CH7_LO_B 0xF04
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#define APU_EDMA3_CMDQ_CH7_LO_C 0xF08
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#define APU_EDMA3_CMDQ_CH7_LO_D 0xF0C
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#define APU_EDMA3_CMDQ_CH7_LO_E 0xF10
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#define APU_EDMA3_CMDQ_CH7_LO_F 0xF14
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#define APU_EDMA3_CMDQ_CH7_HI_A 0xF80
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#define APU_EDMA3_CMDQ_CH7_HI_B 0xF84
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#define APU_EDMA3_CMDQ_CH7_HI_C 0xF88
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#define APU_EDMA3_CMDQ_CH7_HI_D 0xF8C
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#define APU_EDMA3_CMDQ_CH7_HI_E 0xF90
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#define APU_EDMA3_CMDQ_CH7_HI_F 0xF94
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static inline unsigned int edma_read_reg32(void __iomem *edma_base,
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unsigned int offset)
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{
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return readl(edma_base + offset);
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}
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static inline void edma_write_reg32(void __iomem *edma_base,
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unsigned int offset,
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unsigned int val)
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{
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writel(val, edma_base + offset);
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}
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static inline void edma_set_reg32(void __iomem *edma_base, unsigned int offset,
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unsigned int bits)
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{
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edma_write_reg32(edma_base, offset,
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(edma_read_reg32(edma_base, offset) | bits));
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}
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static inline void edma_clear_reg32(void __iomem *edma_base,
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unsigned int offset,
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unsigned int bits)
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{
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edma_write_reg32(edma_base, offset,
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(edma_read_reg32(edma_base, offset) & ~bits));
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}
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#endif
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