143 lines
3.9 KiB
C
143 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: JB Tsai <jb.tsai@mediatek.com>
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*/
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#ifndef __EDMA_REG_H__
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#define __EDMA_REG_H__
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#include <linux/kernel.h>
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#include <linux/io.h>
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#define EDMA_REG_SHOW_RANGE 0x150
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#define EDMA_REG_EX_R1 0xC00
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#define EDMA_REG_EX_R2 0xC5C
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#define DESP_WRITE_POINTER_MASK 0x00000030
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#define NUM_DESP_MASK 0x00000007
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#define DESP_NUM_INCR_MASK 0x00070000
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#define DMA_IDLE_MASK 0x00000200
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#define YUVRGB_MAT_MASK 0x7E000000
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#define APU_EDMA2_DESP_OFFSET 0x100
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#define APU_EDMA2_EX_DESP_OFFSET 0x60
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/* APU_EDMA2_CTL_0 */
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#define CLK_ENABLE BIT(0)
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#define DMA_SW_RST BIT(4)
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#define AXI_PROT_EN BIT(12)
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#define RST_PROT_IDLE BIT(14)
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#define EDMA_DESCRIPTOR_MODE BIT(16)
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/* APU_EDMA2_CFG_0 */
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#define EXT_DESP_START BIT(12)
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#define DESP_NUM_INCR BIT(16)
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/* APU_EDMA2_INT_STATUS */
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#define DESP0_DONE_STATUS BIT(0)
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#define DESP1_DONE_STATUS BIT(1)
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#define DESP2_DONE_STATUS BIT(2)
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#define DESP3_DONE_STATUS BIT(3)
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#define EXT_DESP_DONE_STATUS BIT(4)
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#define DESP0_DONE_INT_STATUS BIT(16)
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#define DESP1_DONE_INT_STATUS BIT(17)
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#define DESP2_DONE_INT_STATUS BIT(18)
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#define DESP3_DONE_INT_STATUS BIT(19)
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#define EXT_DESP_DONE_INT_STATUS BIT(20)
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/* APU_EDMA2_EXT_DESP_CFG_0 */
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#define EXT_DESP_INT_ENABLE BIT(16)
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#define DESP0_OUT_FILL_MODE BIT(20)
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#define DESP0_INT_ENABLE BIT(28)
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#define EXT_DESP_USER_IOMMU BIT(12)
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#define DESP0_DMA_AWUSER_IOMMU BIT(6)
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#define DESP0_DMA_ARUSER_IOMMU BIT(1)
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#define APU_EDMA2_CTL_0 0x000
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#define APU_EDMA2_CFG_0 0x004
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#define APU_EDMA2_INT_MASK 0x008
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#define APU_EDMA2_ERR_INT_MASK 0x00C
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#define APU_EDMA2_INT_STATUS 0x010
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#define APU_EDMA2_ERR_STATUS 0x014
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#define APU_EDMA2_FILL_VALUE 0x018
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#define APU_EDMA2_UFBC_CFG_0 0x020
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#define APU_EDMA2_UFBC_CFG_1 0x024
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#define APU_EDMA2_UFBDC_CFG_0 0x030
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#define APU_EDMA2_UFBDC_CFG_1 0x034
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#define APU_EDMA2_UFBDC_INFO_0 0x038
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#define APU_EDMA2_AFBC_DBG_SEL 0x080
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#define APU_EDMA2_UFBC_DBG_INFO 0x084
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#define APU_EDMA2_UFBDC_DBG_INFO 0x088
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#define APU_EDMA2_UFBDC_VCODE_0 0x090
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#define APU_EDMA2_UFBDC_VCODE_1 0x094
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#define APU_EDMA2_UFBDC_VCODE_2 0x098
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#define APU_EDMA2_UFBDC_VCODE_3 0x09C
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#define APU_EDMA2_EXT_DESP_CFG_0 0x0A0
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#define APU_EDMA2_EXT_DESP_CFG_1 0x0A4
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#define APU_EDMA2_PMU_CTL 0x100
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#define APU_EDMA2_DBG_PMU_SEL 0x104
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#define APU_EDMA2_DBG_PMU_INFO 0x108
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#define APU_EDMA2_DESP0_0 0x800
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#define APU_EDMA2_DESP0_4 0x804
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#define APU_EDMA2_DESP0_8 0x808
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#define APU_EDMA2_DESP0_C 0x80C
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#define APU_EDMA2_DESP0_10 0x810
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#define APU_EDMA2_DESP0_14 0x814
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#define APU_EDMA2_DESP0_18 0x818
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#define APU_EDMA2_DESP0_1C 0x81C
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#define APU_EDMA2_DESP0_20 0x820
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#define APU_EDMA2_DESP0_24 0x824
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#define APU_EDMA2_DESP0_28 0x828
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#define APU_EDMA2_DESP0_2C 0x82C
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#define APU_EDMA2_DESP0_30 0x830
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#define APU_EDMA2_DESP0_34 0x834
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#define APU_EDMA2_DESP0_38 0x838
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#define APU_EDMA2_DESP0_3C 0x83C
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#define APU_EDMA2_DESP0_40 0x840
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#define APU_EDMA2_DESP0_44 0x844
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#define APU_EDMA2_DESP0_48 0x848
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#define APU_EDMA2_DESP0_4C 0x84C
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#define APU_EDMA2_DESP0_50 0x850
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#define APU_EDMA2_DESP0_54 0x854
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#define APU_EDMA2_DESP0_58 0x858
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#define APU_EDMA2_DESP0_5C 0x85C
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static inline unsigned int edma_read_reg32(void __iomem *edma_base,
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unsigned int offset)
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{
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return readl(edma_base + offset);
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}
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static inline void edma_write_reg32(void __iomem *edma_base,
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unsigned int offset,
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unsigned int val)
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{
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writel(val, edma_base + offset);
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}
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static inline void edma_set_reg32(void __iomem *edma_base, unsigned int offset,
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unsigned int bits)
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{
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edma_write_reg32(edma_base, offset,
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(edma_read_reg32(edma_base, offset) | bits));
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}
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static inline void edma_clear_reg32(void __iomem *edma_base,
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unsigned int offset,
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unsigned int bits)
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{
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edma_write_reg32(edma_base, offset,
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(edma_read_reg32(edma_base, offset) & ~bits));
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}
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#endif /* __EDMA_REG_H__ */
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