474 lines
13 KiB
C
474 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef __CMDQ_DEF_H__
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#define __CMDQ_DEF_H__
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#include <linux/kernel.h>
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#define CMDQ_DRIVER_DEVICE_NAME "mtk_cmdq"
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/* #define CMDQ_COMMON_ENG_SUPPORT */
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#ifdef CMDQ_COMMON_ENG_SUPPORT
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#include "cmdq_engine_common.h"
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#else
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#include "cmdq_engine.h"
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#endif
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#define CMDQ_SPECIAL_SUBSYS_ADDR (99)
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#define CMDQ_GPR_SUPPORT
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#define CMDQ_PROFILE_MARKER_SUPPORT
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#ifdef CMDQ_PROFILE_MARKER_SUPPORT
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#define CMDQ_MAX_PROFILE_MARKER_IN_TASK (5)
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#endif
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#define CMDQ_INVALID_THREAD (-1)
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#define CMDQ_MAX_THREAD_COUNT (16)
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#define CMDQ_MAX_TASK_IN_THREAD (16)
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#define CMDQ_MAX_READ_SLOT_COUNT (4)
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#define CMDQ_INIT_FREE_TASK_COUNT (8)
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/* Thread that are high-priority (display threads) */
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#define CMDQ_MAX_HIGH_PRIORITY_THREAD_COUNT (7)
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#define CMDQ_MIN_SECURE_THREAD_ID (12)
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#define CMDQ_MAX_SECURE_THREAD_COUNT (3)
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#define CMDQ_MAX_ERROR_COUNT (2)
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#define CMDQ_MAX_RETRY_COUNT (1)
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/* ram optimization related configuration */
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#ifdef CONFIG_MTK_GMO_RAM_OPTIMIZE
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#define CMDQ_MAX_RECORD_COUNT (100)
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#else
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#define CMDQ_MAX_RECORD_COUNT (1024)
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#endif
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#define CMDQ_INITIAL_CMD_BLOCK_SIZE (PAGE_SIZE)
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/* instruction is 64-bit */
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#define CMDQ_INST_SIZE (2 * sizeof(uint32_t))
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#define CMDQ_CMD_BUFFER_SIZE (PAGE_SIZE - 32 * CMDQ_INST_SIZE)
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#define CMDQ_MAX_LOOP_COUNT (1000000)
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#define CMDQ_MAX_INST_CYCLE (27)
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#define CMDQ_MIN_AGE_VALUE (5)
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#define CMDQ_MAX_ERROR_SIZE (8 * 1024)
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#define CMDQ_MAX_TASK_IN_SECURE_THREAD (10)
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/* max value of CMDQ_THR_EXEC_CMD_CNT (value starts from 0) */
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#ifdef CMDQ_USE_LARGE_MAX_COOKIE
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#define CMDQ_MAX_COOKIE_VALUE (0xFFFFFFFF)
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#else
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#define CMDQ_MAX_COOKIE_VALUE (0xFFFF)
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#endif
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#define CMDQ_ARG_A_SUBSYS_MASK (0x001F0000)
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#ifdef CONFIG_MTK_FPGA
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#define CMDQ_DEFAULT_TIMEOUT_MS (10000)
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#else
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#define CMDQ_DEFAULT_TIMEOUT_MS (1000)
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#endif
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#define CMDQ_ACQUIRE_THREAD_TIMEOUT_MS (2000)
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#define CMDQ_PREDUMP_TIMEOUT_MS (200)
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#define CMDQ_PREDUMP_RETRY_COUNT (5)
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#ifdef CONFIG_OF
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#define CMDQ_OF_SUPPORT /* enable device tree support */
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#else
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#undef CMDQ_OF_SUPPORT
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#endif
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#ifndef CONFIG_MTK_FPGA
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#define CMDQ_PWR_AWARE /* FPGA does not have ClkMgr */
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#else
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#undef CMDQ_PWR_AWARE
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#endif
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#ifdef CMDQ_SECURE_PATH_HW_LOCK
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#undef CMDQ_SECURE_PATH_NORMAL_IRQ
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#endif
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/* #define CMDQ_DUMP_GIC (0) */
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/* #define CMDQ_PROFILE_MMP (0) */
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#define CMDQ_DUMP_FIRSTERROR
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/* #define CMDQ_INSTRUCTION_COUNT */
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enum CMDQ_HW_THREAD_PRIORITY_ENUM {
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CMDQ_THR_PRIO_SUPERLOW = 0, /* low priority monitor loop */
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CMDQ_THR_PRIO_NORMAL = 1, /* nomral priority */
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/* trigger loop (enables display mutex) */
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CMDQ_THR_PRIO_DISPLAY_TRIGGER = 2,
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/* display ESD check (every 2 secs) */
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#ifdef CMDQ_SPECIAL_ESD_PRIORITY
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CMDQ_THR_PRIO_DISPLAY_ESD = 3,
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#else
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CMDQ_THR_PRIO_DISPLAY_ESD = 4,
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#endif
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/* display config (every frame) */
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CMDQ_THR_PRIO_DISPLAY_CONFIG = 4,
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/* High priority monitor loop */
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CMDQ_THR_PRIO_SUPERHIGH = 5,
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/* maximum possible priority */
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CMDQ_THR_PRIO_MAX = 7,
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};
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enum CMDQ_SCENARIO_ENUM {
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CMDQ_SCENARIO_JPEG_DEC = 0,
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CMDQ_SCENARIO_PRIMARY_DISP = 1,
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CMDQ_SCENARIO_PRIMARY_MEMOUT = 2,
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CMDQ_SCENARIO_PRIMARY_ALL = 3,
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CMDQ_SCENARIO_SUB_DISP = 4,
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CMDQ_SCENARIO_SUB_MEMOUT = 5,
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CMDQ_SCENARIO_SUB_ALL = 6,
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CMDQ_SCENARIO_MHL_DISP = 7,
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CMDQ_SCENARIO_RDMA0_DISP = 8,
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CMDQ_SCENARIO_RDMA0_COLOR0_DISP = 9,
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CMDQ_SCENARIO_RDMA1_DISP = 10,
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/* Trigger loop scenario does not enable HWs */
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CMDQ_SCENARIO_TRIGGER_LOOP = 11,
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/* client from user space, so the cmd buffer is in user space. */
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CMDQ_SCENARIO_USER_MDP = 12,
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CMDQ_SCENARIO_DEBUG = 13,
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CMDQ_SCENARIO_DEBUG_PREFETCH = 14,
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/* ESD check */
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CMDQ_SCENARIO_DISP_ESD_CHECK = 15,
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/* for screen capture to wait for */
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/* RDMA-done without blocking config thread */
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CMDQ_SCENARIO_DISP_SCREEN_CAPTURE = 16,
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/* notifiy there are some tasks exec done in secure path */
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CMDQ_SCENARIO_SECURE_NOTIFY_LOOP = 17,
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CMDQ_SCENARIO_DISP_PRIMARY_DISABLE_SECURE_PATH = 18,
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CMDQ_SCENARIO_DISP_SUB_DISABLE_SECURE_PATH = 19,
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/* color path request from kernel */
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CMDQ_SCENARIO_DISP_COLOR = 20,
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/* color path request from user sapce */
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CMDQ_SCENARIO_USER_DISP_COLOR = 21,
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/* [phased out]client from user space, */
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/* so the cmd buffer is in user space. */
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CMDQ_SCENARIO_USER_SPACE = 22,
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CMDQ_SCENARIO_DISP_MIRROR_MODE = 23,
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CMDQ_SCENARIO_DISP_CONFIG_AAL = 24,
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CMDQ_SCENARIO_DISP_CONFIG_PRIMARY_GAMMA = 25,
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CMDQ_SCENARIO_DISP_CONFIG_SUB_GAMMA = 26,
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CMDQ_SCENARIO_DISP_CONFIG_PRIMARY_DITHER = 27,
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CMDQ_SCENARIO_DISP_CONFIG_SUB_DITHER = 28,
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CMDQ_SCENARIO_DISP_CONFIG_PRIMARY_PWM = 29,
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CMDQ_SCENARIO_DISP_CONFIG_SUB_PWM = 30,
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CMDQ_SCENARIO_DISP_CONFIG_PRIMARY_PQ = 31,
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CMDQ_SCENARIO_DISP_CONFIG_SUB_PQ = 32,
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CMDQ_SCENARIO_DISP_CONFIG_OD = 33,
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CMDQ_SCENARIO_RDMA2_DISP = 34,
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/* for primary trigger loop enable pre-fetch usage */
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CMDQ_SCENARIO_HIGHP_TRIGGER_LOOP = 35,
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/* for low priority monitor loop to polling bus status */
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CMDQ_SCENARIO_LOWP_TRIGGER_LOOP = 36,
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CMDQ_SCENARIO_KERNEL_CONFIG_GENERAL = 37,
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CMDQ_MAX_SCENARIO_COUNT /* ALWAYS keep at the end */
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};
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enum CMDQ_DATA_REGISTER_ENUM {
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/* Value Reg, we use 32-bit */
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/* Address Reg, we use 64-bit */
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/* Note that R0-R15 and P0-P7 actullay share same memory */
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/* and R1 cannot be used. */
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CMDQ_DATA_REG_JPEG = 0x00, /* R0 */
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CMDQ_DATA_REG_JPEG_DST = 0x11, /* P1 */
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CMDQ_DATA_REG_PQ_COLOR = 0x04, /* R4 */
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CMDQ_DATA_REG_PQ_COLOR_DST = 0x13, /* P3 */
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CMDQ_DATA_REG_2D_SHARPNESS_0 = 0x05, /* R5 */
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CMDQ_DATA_REG_2D_SHARPNESS_0_DST = 0x14, /* P4 */
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CMDQ_DATA_REG_2D_SHARPNESS_1 = 0x0a, /* R10 */
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CMDQ_DATA_REG_2D_SHARPNESS_1_DST = 0x16, /* P6 */
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CMDQ_DATA_REG_DEBUG = 0x0b, /* R11 */
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CMDQ_DATA_REG_DEBUG_DST = 0x17, /* P7 */
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/* sentinel value for invalid register ID */
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CMDQ_DATA_REG_INVALID = -1,
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};
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enum CMDQ_MDP_PA_BASE_ENUM {
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CMDQ_MDP_PA_BASE_MM_MUTEX,
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CMDQ_MAX_MDP_PA_BASE_COUNT, /* ALWAYS keep at the end */
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};
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struct cmdq_event_table {
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u16 event; /* cmdq event enum value */
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const char *event_name;
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const char *dts_name;
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};
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/* CMDQ Events */
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#undef DECLARE_CMDQ_EVENT
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#define DECLARE_CMDQ_EVENT(name_struct, val, dts_name) name_struct = val,
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enum CMDQ_EVENT_ENUM {
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#include "cmdq_event_common.h"
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};
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#undef DECLARE_CMDQ_EVENT
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#undef DECLARE_CMDQ_EVENT
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#define DECLARE_CMDQ_EVENT(event_enum, val, dts_name) \
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{event_enum, #event_enum, #dts_name},
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static struct cmdq_event_table cmdq_events[] = {
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#include "cmdq_event_common.h"
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};
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#undef DECLARE_CMDQ_EVENT
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/* CMDQ subsys */
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#undef DECLARE_CMDQ_SUBSYS
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#define DECLARE_CMDQ_SUBSYS(name_struct, val, grp, dts_name) name_struct = val,
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enum CMDQ_SUBSYS_ENUM {
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#include "cmdq_subsys_common.h"
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/* ALWAYS keep at the end */
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CMDQ_SUBSYS_MAX_COUNT
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};
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#undef DECLARE_CMDQ_SUBSYS
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#define CMDQ_SUBSYS_GRPNAME_MAX (30)
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/* GCE subsys information */
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struct SubsysStruct {
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uint32_t msb;
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int32_t subsysID;
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uint32_t mask;
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char grpName[CMDQ_SUBSYS_GRPNAME_MAX];
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};
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struct cmdqDTSDataStruct {
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/* [Out] GCE event table */
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int32_t eventTable[CMDQ_SYNC_TOKEN_MAX];
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/* [Out] GCE subsys ID table */
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struct SubsysStruct subsys[CMDQ_SUBSYS_MAX_COUNT];
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/* [Out] MDP Base address */
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uint32_t MDPBaseAddress[CMDQ_MAX_MDP_PA_BASE_COUNT];
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};
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/* Custom "wide" pointer type for 64-bit job handle (pointer to VA) */
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/* typedef unsigned long long cmdqJobHandle_t; */
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#define cmdqJobHandle_t unsigned long long
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/* Custom "wide" pointer type for 64-bit */
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/* compatibility. Always cast from uint32_t*. */
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/* typedef unsigned long long cmdqU32Ptr_t; */
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#define cmdqU32Ptr_t unsigned long long
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#define CMDQ_U32_PTR(x) ((uint32_t *)(unsigned long)x)
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struct cmdqReadRegStruct {
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uint32_t count; /* number of entries in regAddresses */
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/* an array of 32-bit register addresses (uint32_t) */
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cmdqU32Ptr_t regAddresses;
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};
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struct cmdqRegValueStruct {
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/* number of entries in result */
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uint32_t count;
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/* array of 32-bit register values (uint32_t). */
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/* in the same order as cmdqReadRegStruct */
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cmdqU32Ptr_t regValues;
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};
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struct cmdqReadAddressStruct {
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uint32_t count; /* [IN] number of entries in result. */
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/* [IN] array of physical addresses to read. */
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/* these value must allocated by CMDQ_IOCTL_ALLOC_WRITE_ADDRESS ioctl */
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/* */
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/* indeed param dmaAddresses should be */
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/* UNSIGNED LONG type for 64 bit kernel. */
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/* Considering our plartform supports max */
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/* 4GB RAM(upper-32bit don't care for SW) */
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/* and consistent common code interface, remain uint32_t type. */
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cmdqU32Ptr_t dmaAddresses;
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/* [OUT] uint32_t values that dmaAddresses point into */
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cmdqU32Ptr_t values;
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};
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/*
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* Secure address metadata:
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* According to handle type, translate handle and replace (_d)th instruciton to
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* 1. sec_addr = hadnle_sec_base_addr(baseHandle) + offset(_b)
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* 2. sec_mva = mva( hadnle_sec_base_addr(baseHandle) + offset(_b) )
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* 3. secure world normal mva = map(baseHandle)
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* . pass normal mva to parameter baseHandle
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* . use case: OVL reads from secure and normal buffers at the same time)
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*/
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enum CMDQ_SEC_ADDR_METADATA_TYPE {
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CMDQ_SAM_H_2_PA = 0, /* sec handle to sec PA */
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CMDQ_SAM_H_2_MVA = 1, /* sec handle to sec MVA */
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/* map normal MVA to secure world */
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CMDQ_SAM_NMVA_2_MVA = 2,
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/* DDP register needs to set opposite value when HDCP fail */
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CMDQ_SAM_DDP_REG_HDCP = 3,
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};
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struct cmdqSecAddrMetadataStruct {
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/* [IN]_d, index of instruction. Update its */
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/* arg_b value to real PA/MVA in secure world */
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uint32_t instrIndex;
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/*
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* Note: Buffer and offset
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*
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* -------------
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* | | |
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* -------------
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* ^ ^ ^ ^
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* A B C D
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*
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* A: baseHandle
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* B: baseHandle + blockOffset
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* C: baseHandle + blockOffset + offset
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* A~B or B~D: size
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*/
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uint32_t type; /* [IN] addr handle type */
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uint64_t baseHandle; /* [IN]_h, secure address handle */
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/* [IN]_b, block offset from handle(PA) to current block(plane) */
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uint32_t blockOffset;
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uint32_t offset; /* [IN]_b, buffser offset to secure handle */
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uint32_t size; /* buffer size */
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uint32_t port; /* hw port id (i.e. M4U port id) */
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uint32_t sec_id;
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uint32_t useSecIdinMeta;
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int32_t ionFd;
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};
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/* tablet use */
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enum CMDQ_DISP_MODE {
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CMDQ_DISP_NON_SUPPORTED_MODE = 0,
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CMDQ_DISP_SINGLE_MODE = 1,
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CMDQ_DISP_VIDEO_MODE = 2,
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CMDQ_MDP_USER_MODE = 3,
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};
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struct cmdqSecDataStruct {
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bool is_secure; /* [IN]true for secure command */
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/* address metadata, used to translate secure */
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/* buffer PA related instruction in secure world */
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uint32_t addrMetadataCount; /* [IN] count of element in addrList */
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/* [IN] array of cmdqSecAddrMetadataStruct */
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cmdqU32Ptr_t addrMetadatas;
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uint32_t addrMetadataMaxCount; /*[Reserved] */
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uint64_t enginesNeedDAPC;
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uint64_t enginesNeedPortSecurity;
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/* [Reserved] This is for CMDQ driver usage itself. Not for client. */
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/* task index in thread's tasklist. -1 for not in tasklist. */
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int32_t waitCookie;
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bool resetExecCnt; /* reset HW thread in SWd */
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uint64_t extension;
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#ifdef CONFIG_MTK_CMDQ_TAB
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/* tablet use */
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enum CMDQ_DISP_MODE secMode;
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/* for MDP to copy HDCP version from srcHandle to dstHandle */
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/* will remove later */
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uint32_t srcHandle;
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uint32_t dstHandle;
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#endif
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};
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struct cmdq_v3_replace_struct {
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/* [IN] count of element in instr_position */
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uint32_t number;
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/* [IN] position of instruction */
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cmdqU32Ptr_t position;
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};
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#ifdef CMDQ_PROFILE_MARKER_SUPPORT
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struct cmdqProfileMarkerStruct {
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uint32_t count;
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/* i.e. cmdqBackupSlotHandle, physical start address of backup slot */
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long long hSlot;
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cmdqU32Ptr_t tag[CMDQ_MAX_PROFILE_MARKER_IN_TASK];
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};
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#endif
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struct cmdqCommandStruct {
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/* [IN] deprecated. will remove in the future. */
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uint32_t scenario;
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/* [IN] task schedule priority. this is NOT HW thread priority. */
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uint32_t priority;
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/* [IN] bit flag of engines used. */
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uint64_t engineFlag;
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/* [IN] pointer to instruction buffer. Use 64-bit for compatibility. */
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/* This must point to an 64-bit aligned uint32_t array */
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cmdqU32Ptr_t pVABase;
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/* [IN] size of instruction buffer, in bytes. */
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uint32_t blockSize;
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/* [IN] request to read register values at the end of command */
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struct cmdqReadRegStruct regRequest;
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/* [OUT] register values of regRequest */
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struct cmdqRegValueStruct regValue;
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/* [IN/OUT] physical addresses to read value */
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struct cmdqReadAddressStruct readAddress;
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/* [IN] secure execution data */
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struct cmdqSecDataStruct secData;
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/* [IN] set to non-zero to enable register debug dump. */
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uint32_t debugRegDump;
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/* [Reserved] This is for CMDQ driver usage itself. */
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/* Not for client. Do not access this field from User Space */
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cmdqU32Ptr_t privateData;
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#ifdef CMDQ_PROFILE_MARKER_SUPPORT
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struct cmdqProfileMarkerStruct profileMarker;
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#endif
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cmdqU32Ptr_t userDebugStr;
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uint32_t userDebugStrLen;
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};
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enum CMDQ_CAP_BITS {
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/* bit 0: TRUE if WFE instruction support */
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/* is ready. FALSE if we need to POLL instead. */
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CMDQ_CAP_WFE = 0,
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};
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/**
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* reply struct for cmdq_sec_cancel_error_task
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*/
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struct cmdqSecCancelTaskResultStruct {
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/* [OUT] */
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bool throwAEE;
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bool hasReset;
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int32_t irqFlag;
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uint32_t errInstr[2];
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uint32_t regValue;
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uint32_t pc;
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};
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#endif /* __CMDQ_DEF_H__ */
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