337 lines
6.9 KiB
C
337 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MT6769_VPU_REG_H_
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#define _MT6769_VPU_REG_H_
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#include <sync_write.h>
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#define CTRL_BASE_OFFSET 0x80000
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#define DEBUG_BASE_OFFSET 0x90000
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#define DEBUG_STACK_SIZE 0x1400
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#define DEBUG_MAIN_CODE_SEG_SIZE_1 0x400
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#define DEBUG_MAIN_CODE_SEG_SIZE_2 0x18000
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#define DEBUG_CODE_SEG_SIZE 0x15400
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#define DEBUG_STACK_BASE_OFFSET \
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(0x40000 - DEBUG_STACK_SIZE) /*should sync with Jackie*/
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/* common macro definitions */
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#define F_REG(base, offset) \
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(*((unsigned int *) ((uintptr_t)base + offset)))
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#define F_VAL(val, msb, lsb) \
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((msb - lsb > 30) ? val : (((val)&((1<<(msb-lsb+1))-1))<<lsb))
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#define F_MSK(msb, lsb) \
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F_VAL(0xffffffff, msb, lsb)
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#define F_BIT_SET(bit) (1<<(bit))
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#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
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#define VPU_SET_BIT(reg, bit) \
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((*(unsigned int *)((uintptr_t)reg)) |= (unsigned int)(1 << (bit)))
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#define VPU_CLR_BIT(reg, bit) \
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((*(unsigned int *)((uintptr_t)reg)) &= ~((unsigned int)(1 << (bit))))
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static inline unsigned int vpu_read_reg32(
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unsigned long vpu_base, unsigned int offset)
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{
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return ioread32((void *) (vpu_base + offset));
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}
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static inline void vpu_write_reg32(
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unsigned long vpu_base, unsigned int offset, unsigned int val)
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{
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mt_reg_sync_writel(val, (void *) (vpu_base + offset));
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}
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/* Spare Register - Enum */
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enum {
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VPU_CMD_DO_EXIT = 0x00,
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VPU_CMD_DO_LOADER = 0x01,
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VPU_CMD_DO_DECRYPT = 0x02,
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VPU_CMD_DO_PASS1_DL = 0x10,
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VPU_CMD_DO_PASS2_DL = 0x11,
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VPU_CMD_DO_D2D = 0x22,
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VPU_CMD_SET_DEBUG = 0x40,
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VPU_CMD_SET_MPU = 0x41,
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VPU_CMD_SET_FTRACE_LOG = 0x42,
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VPU_CMD_GET_SWVER = 0x81,
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VPU_CMD_GET_ALGO = 0x82,
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/* Extend for test */
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VPU_CMD_EXT_BUSY = 0xF0
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};
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enum {
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VPU_STATE_NOT_READY = 0x00,
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VPU_STATE_READY = 0x01,
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VPU_STATE_IDLE = 0x02,
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VPU_STATE_BUSY = 0x04,
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VPU_STATE_ERROR = 0x08,
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VPU_STATE_TERMINATED = 0x10
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};
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enum {
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VPU_REQ_DO_CHECK_STATE = 0x100,
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VPU_REQ_DO_DUMP_LOG = 0x101,
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VPU_REQ_DO_CLOSED_FILE = 0x102
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};
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enum vpu_reg {
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/* module vpu */
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REG_CG_CON,
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REG_CG_SET,
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REG_CG_CLR,
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REG_SW_RST,
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REG_MBIST_MODE,
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REG_MBIST_CTL,
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REG_RP_OK0,
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REG_RP_OK1,
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/*REG_RP_OK2,*/
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REG_RP_FAIL0,
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REG_RP_FAIL1,
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/*REG_RP_FAIL2,*/
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REG_MBIST_FAIL0,
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REG_MBIST_FAIL1,
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/*REG_MBIST_FAIL2,*/
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REG_MBIST_DONE,
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REG_SRAM_DELSEL0,
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REG_SRAM_DELSEL1,
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REG_RP_RST,
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REG_RP_CON,
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REG_RP_PRE_FUSE,
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REG_SLEEP_SRAM_CTL,
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REG_SPARE0,
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REG_SPARE1,
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REG_SPARE2,
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REG_SPARE3,
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REG_EVENT_TRIG,
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REG_DONE_ST,
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REG_CTRL,
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REG_XTENSA_INT,
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REG_CTL_XTENSA_INT,
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REG_CTL_XTENSA_INT_CLR,
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REG_INT_MASK,
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REG_AXI_DEFAULT0,
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REG_AXI_DEFAULT1,
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REG_AXI_DEFAULT2,
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REG_AXI_DEFAULT3,
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REG_CABGEN_CTL,
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REG_XTENSA_INFO00,
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REG_XTENSA_INFO01,
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REG_XTENSA_INFO02,
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REG_XTENSA_INFO03,
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REG_XTENSA_INFO04,
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REG_XTENSA_INFO05,
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REG_XTENSA_INFO06,
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REG_XTENSA_INFO07,
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REG_XTENSA_INFO08,
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REG_XTENSA_INFO09,
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REG_XTENSA_INFO10,
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REG_XTENSA_INFO11,
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REG_XTENSA_INFO12,
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REG_XTENSA_INFO13,
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REG_XTENSA_INFO14,
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REG_XTENSA_INFO15,
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REG_XTENSA_INFO16,
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REG_XTENSA_INFO17,
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REG_XTENSA_INFO18,
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REG_XTENSA_INFO19,
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REG_XTENSA_INFO20,
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REG_XTENSA_INFO21,
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REG_XTENSA_INFO22,
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REG_XTENSA_INFO23,
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REG_XTENSA_INFO24,
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REG_XTENSA_INFO25,
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REG_XTENSA_INFO26,
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REG_XTENSA_INFO27,
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REG_XTENSA_INFO28,
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REG_XTENSA_INFO29,
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REG_XTENSA_INFO30,
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REG_XTENSA_INFO31,
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REG_DEBUG_INFO00,
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REG_DEBUG_INFO01,
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REG_DEBUG_INFO02,
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REG_DEBUG_INFO03,
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REG_DEBUG_INFO04,
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REG_DEBUG_INFO05,
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REG_DEBUG_INFO06,
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REG_DEBUG_INFO07,
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REG_XTENSA_ALTRESETVEC,
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REG_CAM_INT,
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REG_CAM_INT_CLR,
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VPU_NUM_REGS
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};
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enum vpu_reg_field {
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/* module vpu */
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FLD_IPU_CG,
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FLD_AXI_M_CG,
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FLD_JTAG_CG,
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FLD_IPU_CG_SET,
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FLD_AXI_M_CG_SET,
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FLD_JTAG_CG_SET,
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FLD_IPU_CG_CLR,
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FLD_AXI_M_CG_CLR,
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FLD_JTAG_CG_CLR,
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FLD_OCDHALTONRESET,
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FLD_IPU_D_RST,
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FLD_IPU_B_RST,
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FLD_IPU_APB_RST,
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FLD_AXI_M_RST,
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FLD_IPU_HW_RST,
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FLD_CORE_MBIST_MODE,
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FLD_CORE_MBIST_RSTB,
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FLD_CORE_MBIST_BACKGROUND,
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FLD_CORE_MBIST_BSEL,
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FLD_CORE_MBIST_RP_OK_0,
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FLD_CORE_MBIST_RP_OK_1,
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FLD_CORE_MBIST_RP_FAIL_0,
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FLD_CORE_MBIST_RP_FAIL_1,
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FLD_CORE_MBIST_FAIL_0,
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FLD_CORE_MBIST_FAIL_1,
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FLD_CORE_MBIST_DONE,
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FLD_CORE_SRAM_DELSEL_0,
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FLD_CORE_SRAM_DELSEL_1,
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FLD_CORE_RP_RSTB,
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FLD_CORE_RP_CON,
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FLD_CORE_RP_PRE_FUSE,
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FLD_CORE_SRAM_SLEEP_W,
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FLD_CORE_SRAM_SLEEP_R,
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FLD_CORE_SRAM_SLEEP_INV,
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FLD_CORE_SRAM_SLEEP_TEST,
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FLD_CORE_SRAM_HDEN,
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FLD_CORE_SPARE0,
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FLD_CORE_SPARE1,
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FLD_CORE_SPARE2,
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FLD_CORE_SPARE3,
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FLD_PWAITMODE,
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FLD_BREAK_IN_ACK,
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FLD_BREAK_OUT,
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FLD_XOCDMODE,
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FLD_P_DEBUG_ENABLE,
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FLD_STROBE,
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FLD_SRAM_CONFIGURE,
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FLD_PBCLK_ENABLE,
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FLD_RUN_STALL,
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FLD_TRIG_IN_DMA,
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FLD_BREAK_OUT_ACK,
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FLD_BREAK_IN,
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FLD_STATE_VECTOR_SELECT,
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FLD_TIE2APB_GATED_ENABLE,
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FLD_PIF_GATED,
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FLD_PRID,
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FLD_NMI,
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FLD_APMCU_INT,
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FLD_CTL_INT,
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FLD_CTL_INT_CLR,
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FLD_IPU2CAM_INT_MASK,
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FLD_APMCU_INT_MASK,
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FLD_CTL_INT_MASK,
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FLD_ARUSER_8_4,
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FLD_AWUSER_8_4,
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FLD_ARDOMAIN,
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FLD_ARFLUSH,
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FLD_ARULTRA,
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FLD_AWDOMAIN,
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FLD_AWFLUSH,
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FLD_AWULTRA,
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FLD_ARUSER_IDMA_8_4,
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FLD_AWUSER_IDMA_8_4,
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FLD_ARDOMAIN_IDMA,
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FLD_ARFLUSH_IDMA,
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FLD_ARULTRA_IDMA,
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FLD_AWDOMAIN_IDMA,
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FLD_AWFLUSH_IDMA,
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FLD_AWULTRA_IDMA,
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FLD_SPIDEN,
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FLD_SPNIDEN,
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FLD_NIDEN,
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FLD_DBG_EN,
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FLD_CABGEN2TO1_SLICE_O_ARTHRES,
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FLD_CABGEN2TO1_SLICE_O_AWTHRES,
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FLD_CABGEN2TO1_SLICE_MI0_OUTSTANDING_EXTEND_EN,
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FLD_CABGEN2TO1_SLICE_MI0_QOS_ON,
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FLD_CABGEN2TO1_SLICE_CG_DIS,
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FLD_CABGEN2TO1_SLICE_PCLK_EN,
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FLD_XTENSA_INFO00,
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FLD_XTENSA_INFO01,
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FLD_XTENSA_INFO02,
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FLD_XTENSA_INFO03,
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FLD_XTENSA_INFO04,
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FLD_XTENSA_INFO05,
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FLD_XTENSA_INFO06,
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FLD_XTENSA_INFO07,
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FLD_XTENSA_INFO08,
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FLD_XTENSA_INFO09,
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FLD_XTENSA_INFO10,
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FLD_XTENSA_INFO11,
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FLD_XTENSA_INFO12,
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FLD_XTENSA_INFO13,
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FLD_XTENSA_INFO14,
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FLD_XTENSA_INFO15,
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FLD_XTENSA_INFO16,
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FLD_XTENSA_INFO17,
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FLD_XTENSA_INFO18,
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FLD_XTENSA_INFO19,
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FLD_XTENSA_INFO20,
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FLD_XTENSA_INFO21,
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FLD_XTENSA_INFO22,
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FLD_XTENSA_INFO23,
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FLD_XTENSA_INFO24,
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FLD_XTENSA_INFO25,
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FLD_XTENSA_INFO26,
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FLD_XTENSA_INFO27,
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FLD_XTENSA_INFO28,
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FLD_XTENSA_INFO29,
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FLD_XTENSA_INFO30,
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FLD_XTENSA_INFO31,
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FLD_P_DEBUG_DATA,
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FLD_IPU_INFO_01,
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FLD_P_DEBUG_STATUS,
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FLD_P_DEBUG_INB_PIF,
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FLD_P_DEBUG_INST,
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FLD_P_DEBUG_LS0_STAT,
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FLD_P_DEBUG_LS1_STAT,
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FLD_P_DEBUG_PC,
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FLD_IPU_INFO_06,
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FLD_PSLVERR,
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FLD_IRAM0_LOAD_STORE,
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FLD_P_FAULT_INFO_VALID,
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FLD_P_FATAL_ERROR,
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FLD_DOUBLE_EXCEPTION_ERROR,
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FLD_TRIG_OUT_IDMA,
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FLD_P_FAULT_INFO,
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FLD_CORE_XTENSA_ALTRESETVEC,
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FLD_IPU2CAM_INT,
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FLD_IPU2CAM_INT_WRITE_ONE_CLEAR,
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VPU_NUM_REG_FIELDS
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};
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struct vpu_reg_desc {
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enum vpu_reg reg;
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char *name;
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uint32_t offset;
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uint8_t size;
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};
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struct vpu_reg_field_desc {
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enum vpu_reg reg;
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enum vpu_reg_field field;
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char *name;
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uint8_t msb;
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uint8_t lsb;
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};
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extern struct vpu_reg_desc g_vpu_reg_descs[VPU_NUM_REGS];
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extern struct vpu_reg_field_desc g_vpu_reg_field_descs[VPU_NUM_REG_FIELDS];
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uint32_t vpu_read_field(int core, enum vpu_reg_field f);
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void vpu_write_field(int core, enum vpu_reg_field f, uint32_t v);
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#endif
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