328 lines
8.2 KiB
C
328 lines
8.2 KiB
C
/*
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* Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _ENIC_H_
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#define _ENIC_H_
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#include "vnic_enet.h"
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#include "vnic_dev.h"
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#include "vnic_wq.h"
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#include "vnic_rq.h"
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#include "vnic_cq.h"
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#include "vnic_intr.h"
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#include "vnic_stats.h"
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#include "vnic_nic.h"
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#include "vnic_rss.h"
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#include <linux/irq.h>
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#define DRV_NAME "enic"
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#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"
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#define DRV_VERSION "2.3.0.53"
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#define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc"
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#define ENIC_BARS_MAX 6
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#define ENIC_WQ_MAX 8
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#define ENIC_RQ_MAX 8
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#define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
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#define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
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#define ENIC_WQ_NAPI_BUDGET 256
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#define ENIC_AIC_LARGE_PKT_DIFF 3
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struct enic_msix_entry {
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int requested;
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char devname[IFNAMSIZ + 8];
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irqreturn_t (*isr)(int, void *);
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void *devid;
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cpumask_var_t affinity_mask;
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};
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/* Store only the lower range. Higher range is given by fw. */
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struct enic_intr_mod_range {
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u32 small_pkt_range_start;
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u32 large_pkt_range_start;
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};
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struct enic_intr_mod_table {
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u32 rx_rate;
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u32 range_percent;
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};
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#define ENIC_MAX_LINK_SPEEDS 3
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#define ENIC_LINK_SPEED_10G 10000
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#define ENIC_LINK_SPEED_4G 4000
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#define ENIC_LINK_40G_INDEX 2
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#define ENIC_LINK_10G_INDEX 1
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#define ENIC_LINK_4G_INDEX 0
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#define ENIC_RX_COALESCE_RANGE_END 125
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#define ENIC_AIC_TS_BREAK 100
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struct enic_rx_coal {
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u32 small_pkt_range_start;
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u32 large_pkt_range_start;
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u32 range_end;
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u32 use_adaptive_rx_coalesce;
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};
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/* priv_flags */
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#define ENIC_SRIOV_ENABLED (1 << 0)
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/* enic port profile set flags */
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#define ENIC_PORT_REQUEST_APPLIED (1 << 0)
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#define ENIC_SET_REQUEST (1 << 1)
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#define ENIC_SET_NAME (1 << 2)
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#define ENIC_SET_INSTANCE (1 << 3)
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#define ENIC_SET_HOST (1 << 4)
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struct enic_port_profile {
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u32 set;
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u8 request;
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char name[PORT_PROFILE_MAX];
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u8 instance_uuid[PORT_UUID_MAX];
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u8 host_uuid[PORT_UUID_MAX];
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u8 vf_mac[ETH_ALEN];
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u8 mac_addr[ETH_ALEN];
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};
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/* enic_rfs_fltr_node - rfs filter node in hash table
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* @@keys: IPv4 5 tuple
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* @flow_id: flow_id of clsf filter provided by kernel
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* @fltr_id: filter id of clsf filter returned by adaptor
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* @rq_id: desired rq index
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* @node: hlist_node
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*/
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struct enic_rfs_fltr_node {
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struct flow_keys keys;
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u32 flow_id;
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u16 fltr_id;
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u16 rq_id;
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struct hlist_node node;
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};
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/* enic_rfs_flw_tbl - rfs flow table
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* @max: Maximum number of filters vNIC supports
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* @free: Number of free filters available
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* @toclean: hash table index to clean next
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* @ht_head: hash table list head
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* @lock: spin lock
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* @rfs_may_expire: timer function for enic_rps_may_expire_flow
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*/
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struct enic_rfs_flw_tbl {
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u16 max;
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int free;
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#define ENIC_RFS_FLW_BITSHIFT (10)
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#define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)
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u16 toclean:ENIC_RFS_FLW_BITSHIFT;
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struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];
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spinlock_t lock;
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struct timer_list rfs_may_expire;
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};
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struct vxlan_offload {
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u16 vxlan_udp_port_number;
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u8 patch_level;
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u8 flags;
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};
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/* Per-instance private data structure */
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struct enic {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct vnic_enet_config config;
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struct vnic_dev_bar bar[ENIC_BARS_MAX];
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struct vnic_dev *vdev;
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struct timer_list notify_timer;
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struct work_struct reset;
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struct work_struct tx_hang_reset;
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struct work_struct change_mtu_work;
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struct msix_entry msix_entry[ENIC_INTR_MAX];
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struct enic_msix_entry msix[ENIC_INTR_MAX];
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u32 msg_enable;
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spinlock_t devcmd_lock;
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u8 mac_addr[ETH_ALEN];
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unsigned int flags;
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unsigned int priv_flags;
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unsigned int mc_count;
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unsigned int uc_count;
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u32 port_mtu;
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struct enic_rx_coal rx_coalesce_setting;
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u32 rx_coalesce_usecs;
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u32 tx_coalesce_usecs;
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#ifdef CONFIG_PCI_IOV
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u16 num_vfs;
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#endif
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spinlock_t enic_api_lock;
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bool enic_api_busy;
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struct enic_port_profile *pp;
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/* work queue cache line section */
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____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
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spinlock_t wq_lock[ENIC_WQ_MAX];
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unsigned int wq_count;
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u16 loop_enable;
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u16 loop_tag;
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/* receive queue cache line section */
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____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
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unsigned int rq_count;
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struct vxlan_offload vxlan;
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u64 rq_truncated_pkts;
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u64 rq_bad_fcs;
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struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];
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/* interrupt resource cache line section */
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____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
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unsigned int intr_count;
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u32 __iomem *legacy_pba; /* memory-mapped */
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/* completion queue cache line section */
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____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
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unsigned int cq_count;
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struct enic_rfs_flw_tbl rfs_h;
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u32 rx_copybreak;
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u8 rss_key[ENIC_RSS_LEN];
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struct vnic_gen_stats gen_stats;
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};
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static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)
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{
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struct enic *enic = vdev->priv;
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return enic->netdev;
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}
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/* wrappers function for kernel log
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*/
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#define vdev_err(vdev, fmt, ...) \
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dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
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#define vdev_warn(vdev, fmt, ...) \
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dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
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#define vdev_info(vdev, fmt, ...) \
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dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
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#define vdev_neterr(vdev, fmt, ...) \
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netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
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#define vdev_netwarn(vdev, fmt, ...) \
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netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
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#define vdev_netinfo(vdev, fmt, ...) \
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netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
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static inline struct device *enic_get_dev(struct enic *enic)
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{
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return &(enic->pdev->dev);
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}
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static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)
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{
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return rq;
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}
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static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
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{
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return enic->rq_count + wq;
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}
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static inline unsigned int enic_legacy_io_intr(void)
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{
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return 0;
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}
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static inline unsigned int enic_legacy_err_intr(void)
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{
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return 1;
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}
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static inline unsigned int enic_legacy_notify_intr(void)
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{
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return 2;
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}
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static inline unsigned int enic_msix_rq_intr(struct enic *enic,
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unsigned int rq)
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{
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return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;
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}
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static inline unsigned int enic_msix_wq_intr(struct enic *enic,
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unsigned int wq)
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{
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return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;
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}
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static inline unsigned int enic_msix_err_intr(struct enic *enic)
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{
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return enic->rq_count + enic->wq_count;
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}
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static inline unsigned int enic_msix_notify_intr(struct enic *enic)
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{
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return enic->rq_count + enic->wq_count + 1;
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}
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static inline bool enic_is_err_intr(struct enic *enic, int intr)
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{
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switch (vnic_dev_get_intr_mode(enic->vdev)) {
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case VNIC_DEV_INTR_MODE_INTX:
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return intr == enic_legacy_err_intr();
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case VNIC_DEV_INTR_MODE_MSIX:
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return intr == enic_msix_err_intr(enic);
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case VNIC_DEV_INTR_MODE_MSI:
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default:
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return false;
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}
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}
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static inline bool enic_is_notify_intr(struct enic *enic, int intr)
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{
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switch (vnic_dev_get_intr_mode(enic->vdev)) {
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case VNIC_DEV_INTR_MODE_INTX:
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return intr == enic_legacy_notify_intr();
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case VNIC_DEV_INTR_MODE_MSIX:
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return intr == enic_msix_notify_intr(enic);
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case VNIC_DEV_INTR_MODE_MSI:
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default:
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return false;
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}
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}
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static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)
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{
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if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) {
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net_warn_ratelimited("%s: PCI dma mapping failed!\n",
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enic->netdev->name);
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enic->gen_stats.dma_map_error++;
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return -ENOMEM;
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}
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return 0;
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}
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void enic_reset_addr_lists(struct enic *enic);
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int enic_sriov_enabled(struct enic *enic);
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int enic_is_valid_vf(struct enic *enic, int vf);
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int enic_is_dynamic(struct enic *enic);
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void enic_set_ethtool_ops(struct net_device *netdev);
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int __enic_set_rsskey(struct enic *enic);
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#endif /* _ENIC_H_ */
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