429 lines
13 KiB
C
429 lines
13 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _CE_H_
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#define _CE_H_
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#include "hif.h"
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#define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
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/* Descriptor rings must be aligned to this boundary */
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#define CE_DESC_RING_ALIGN 8
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#define CE_SEND_FLAG_GATHER 0x00010000
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/*
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* Copy Engine support: low-level Target-side Copy Engine API.
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* This is a hardware access layer used by code that understands
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* how to use copy engines.
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*/
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struct ath10k_ce_pipe;
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#define CE_DESC_FLAGS_GATHER (1 << 0)
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#define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
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#define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
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#define CE_DESC_FLAGS_GET_MASK GENMASK(4, 0)
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#define CE_DESC_37BIT_ADDR_MASK GENMASK_ULL(37, 0)
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/* Following desc flags are used in QCA99X0 */
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#define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2)
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#define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3)
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#define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
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#define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb
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#define CE_DDR_RRI_MASK GENMASK(15, 0)
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#define CE_DDR_DRRI_SHIFT 16
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struct ce_desc {
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__le32 addr;
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__le16 nbytes;
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__le16 flags; /* %CE_DESC_FLAGS_ */
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};
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struct ce_desc_64 {
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__le64 addr;
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__le16 nbytes; /* length in register map */
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__le16 flags; /* fw_metadata_high */
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__le32 toeplitz_hash_result;
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};
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#define CE_DESC_SIZE sizeof(struct ce_desc)
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#define CE_DESC_SIZE_64 sizeof(struct ce_desc_64)
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struct ath10k_ce_ring {
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/* Number of entries in this ring; must be power of 2 */
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unsigned int nentries;
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unsigned int nentries_mask;
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/*
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* For dest ring, this is the next index to be processed
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* by software after it was/is received into.
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*
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* For src ring, this is the last descriptor that was sent
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* and completion processed by software.
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*
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* Regardless of src or dest ring, this is an invariant
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* (modulo ring size):
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* write index >= read index >= sw_index
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*/
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unsigned int sw_index;
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/* cached copy */
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unsigned int write_index;
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/*
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* For src ring, this is the next index not yet processed by HW.
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* This is a cached copy of the real HW index (read index), used
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* for avoiding reading the HW index register more often than
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* necessary.
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* This extends the invariant:
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* write index >= read index >= hw_index >= sw_index
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*
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* For dest ring, this is currently unused.
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*/
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/* cached copy */
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unsigned int hw_index;
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/* Start of DMA-coherent area reserved for descriptors */
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/* Host address space */
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void *base_addr_owner_space_unaligned;
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/* CE address space */
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u32 base_addr_ce_space_unaligned;
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/*
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* Actual start of descriptors.
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* Aligned to descriptor-size boundary.
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* Points into reserved DMA-coherent area, above.
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*/
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/* Host address space */
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void *base_addr_owner_space;
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/* CE address space */
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u32 base_addr_ce_space;
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char *shadow_base_unaligned;
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struct ce_desc_64 *shadow_base;
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/* keep last */
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void *per_transfer_context[0];
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};
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struct ath10k_ce_pipe {
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struct ath10k *ar;
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unsigned int id;
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unsigned int attr_flags;
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u32 ctrl_addr;
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void (*send_cb)(struct ath10k_ce_pipe *);
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void (*recv_cb)(struct ath10k_ce_pipe *);
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unsigned int src_sz_max;
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struct ath10k_ce_ring *src_ring;
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struct ath10k_ce_ring *dest_ring;
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const struct ath10k_ce_ops *ops;
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};
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/* Copy Engine settable attributes */
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struct ce_attr;
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struct ath10k_bus_ops {
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u32 (*read32)(struct ath10k *ar, u32 offset);
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void (*write32)(struct ath10k *ar, u32 offset, u32 value);
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int (*get_num_banks)(struct ath10k *ar);
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};
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static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
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{
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return (struct ath10k_ce *)ar->ce_priv;
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}
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struct ath10k_ce {
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/* protects CE info */
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spinlock_t ce_lock;
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const struct ath10k_bus_ops *bus_ops;
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struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
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u32 *vaddr_rri;
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dma_addr_t paddr_rri;
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};
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/*==================Send====================*/
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/* ath10k_ce_send flags */
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#define CE_SEND_FLAG_BYTE_SWAP 1
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/*
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* Queue a source buffer to be sent to an anonymous destination buffer.
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* ce - which copy engine to use
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* buffer - address of buffer
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* nbytes - number of bytes to send
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* transfer_id - arbitrary ID; reflected to destination
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* flags - CE_SEND_FLAG_* values
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* Returns 0 on success; otherwise an error status.
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*
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* Note: If no flags are specified, use CE's default data swap mode.
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*
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* Implementation note: pushes 1 buffer to Source ring
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*/
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int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_send_context,
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dma_addr_t buffer,
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unsigned int nbytes,
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/* 14 bits */
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unsigned int transfer_id,
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unsigned int flags);
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int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_context,
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dma_addr_t buffer,
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unsigned int nbytes,
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unsigned int transfer_id,
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unsigned int flags);
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void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
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int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
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/*==================Recv=======================*/
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int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
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int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr);
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void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
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/* recv flags */
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/* Data is byte-swapped */
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#define CE_RECV_FLAG_SWAPPED 1
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/*
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* Supply data for the next completed unprocessed receive descriptor.
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* Pops buffer from Dest ring.
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*/
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int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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unsigned int *nbytesp);
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/*
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* Supply data for the next completed unprocessed send descriptor.
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* Pops 1 completed send buffer from Source ring.
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*/
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int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp);
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int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp);
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/*==================CE Engine Initialization=======================*/
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int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
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const struct ce_attr *attr);
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void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
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int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
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const struct ce_attr *attr);
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void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
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/*==================CE Engine Shutdown=======================*/
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/*
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* Support clean shutdown by allowing the caller to revoke
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* receive buffers. Target DMA must be stopped before using
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* this API.
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*/
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int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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dma_addr_t *bufferp);
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int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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unsigned int *nbytesp);
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/*
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* Support clean shutdown by allowing the caller to cancel
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* pending sends. Target DMA must be stopped before using
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* this API.
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*/
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int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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dma_addr_t *bufferp,
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unsigned int *nbytesp,
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unsigned int *transfer_idp);
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/*==================CE Interrupt Handlers====================*/
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void ath10k_ce_per_engine_service_any(struct ath10k *ar);
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void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
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int ath10k_ce_disable_interrupts(struct ath10k *ar);
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void ath10k_ce_enable_interrupts(struct ath10k *ar);
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void ath10k_ce_dump_registers(struct ath10k *ar,
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struct ath10k_fw_crash_data *crash_data);
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void ath10k_ce_alloc_rri(struct ath10k *ar);
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void ath10k_ce_free_rri(struct ath10k *ar);
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/* ce_attr.flags values */
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/* Use NonSnooping PCIe accesses? */
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#define CE_ATTR_NO_SNOOP 1
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/* Byte swap data words */
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#define CE_ATTR_BYTE_SWAP_DATA 2
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/* Swizzle descriptors? */
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#define CE_ATTR_SWIZZLE_DESCRIPTORS 4
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/* no interrupt on copy completion */
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#define CE_ATTR_DIS_INTR 8
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/* Attributes of an instance of a Copy Engine */
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struct ce_attr {
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/* CE_ATTR_* values */
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unsigned int flags;
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/* #entries in source ring - Must be a power of 2 */
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unsigned int src_nentries;
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/*
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* Max source send size for this CE.
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* This is also the minimum size of a destination buffer.
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*/
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unsigned int src_sz_max;
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/* #entries in destination ring - Must be a power of 2 */
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unsigned int dest_nentries;
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void (*send_cb)(struct ath10k_ce_pipe *);
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void (*recv_cb)(struct ath10k_ce_pipe *);
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};
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struct ath10k_ce_ops {
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struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar,
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u32 ce_id,
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const struct ce_attr *attr);
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struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar,
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u32 ce_id,
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const struct ce_attr *attr);
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int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr);
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int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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u32 *nbytesp);
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int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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dma_addr_t *nbytesp);
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void (*ce_extract_desc_data)(struct ath10k *ar,
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struct ath10k_ce_ring *src_ring,
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u32 sw_index, dma_addr_t *bufferp,
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u32 *nbytesp, u32 *transfer_idp);
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void (*ce_free_pipe)(struct ath10k *ar, int ce_id);
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int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe,
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void *per_transfer_context,
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dma_addr_t buffer, u32 nbytes,
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u32 transfer_id, u32 flags);
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};
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static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
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{
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return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
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}
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#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \
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- CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
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#define CE_SRC_RING_TO_DESC(baddr, idx) \
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(&(((struct ce_desc *)baddr)[idx]))
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#define CE_DEST_RING_TO_DESC(baddr, idx) \
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(&(((struct ce_desc *)baddr)[idx]))
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#define CE_SRC_RING_TO_DESC_64(baddr, idx) \
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(&(((struct ce_desc_64 *)baddr)[idx]))
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#define CE_DEST_RING_TO_DESC_64(baddr, idx) \
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(&(((struct ce_desc_64 *)baddr)[idx]))
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/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
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#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
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(((int)(toidx) - (int)(fromidx)) & (nentries_mask))
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#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
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#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
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(((idx) + (num)) & (nentries_mask))
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
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ar->regs->ce_wrap_intr_sum_host_msi_lsb
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
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ar->regs->ce_wrap_intr_sum_host_msi_mask
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
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(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
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CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
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#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
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#define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0))
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static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
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{
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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if (!ar->hw_params.per_ce_irq)
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return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
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ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
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CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
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else
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return CE_INTERRUPT_SUMMARY;
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}
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/* Host software's Copy Engine configuration. */
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#define CE_ATTR_FLAGS 0
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/*
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* Configuration information for a Copy Engine pipe.
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* Passed from Host to Target during startup (one per CE).
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*
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* NOTE: Structure is shared between Host software and Target firmware!
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*/
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struct ce_pipe_config {
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__le32 pipenum;
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__le32 pipedir;
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__le32 nentries;
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__le32 nbytes_max;
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__le32 flags;
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__le32 reserved;
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};
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/*
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* Directions for interconnect pipe configuration.
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* These definitions may be used during configuration and are shared
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* between Host and Target.
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*
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* Pipe Directions are relative to the Host, so PIPEDIR_IN means
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* "coming IN over air through Target to Host" as with a WiFi Rx operation.
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* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
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* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
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* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
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* over the interconnect.
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*/
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#define PIPEDIR_NONE 0
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#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
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#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
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#define PIPEDIR_INOUT 3 /* bidirectional */
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/* Establish a mapping between a service/direction and a pipe. */
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struct service_to_pipe {
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__le32 service_id;
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__le32 pipedir;
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__le32 pipenum;
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};
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#endif /* _CE_H_ */
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