131 lines
3.9 KiB
Plaintext
131 lines
3.9 KiB
Plaintext
Spear PCIe Gadget Driver:
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Author
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=============
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Pratyush Anand (pratyush.anand@gmail.com)
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Location
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============
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driver/misc/spear13xx_pcie_gadget.c
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Supported Chip:
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===================
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SPEAr1300
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SPEAr1310
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Menuconfig option:
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==========================
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Device Drivers
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Misc devices
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PCIe gadget support for SPEAr13XX platform
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purpose
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===========
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This driver has several nodes which can be read/written by configfs interface.
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Its main purpose is to configure selected dual mode PCIe controller as device
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and then program its various registers to configure it as a particular device
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type. This driver can be used to show spear's PCIe device capability.
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Description of different nodes:
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=================================
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read behavior of nodes:
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------------------------------
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link :gives ltssm status.
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int_type :type of supported interrupt
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no_of_msi :zero if MSI is not enabled by host. A positive value is the
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number of MSI vector granted.
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vendor_id :returns programmed vendor id (hex)
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device_id :returns programmed device id(hex)
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bar0_size: :returns size of bar0 in hex.
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bar0_address :returns address of bar0 mapped area in hex.
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bar0_rw_offset :returns offset of bar0 for which bar0_data will return value.
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bar0_data :returns data at bar0_rw_offset.
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write behavior of nodes:
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------------------------------
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link :write UP to enable ltsmm DOWN to disable
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int_type :write interrupt type to be configured and (int_type could be
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INTA, MSI or NO_INT). Select MSI only when you have programmed
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no_of_msi node.
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no_of_msi :number of MSI vector needed.
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inta :write 1 to assert INTA and 0 to de-assert.
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send_msi :write MSI vector to be sent.
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vendor_id :write vendor id(hex) to be programmed.
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device_id :write device id(hex) to be programmed.
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bar0_size :write size of bar0 in hex. default bar0 size is 1000 (hex)
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bytes.
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bar0_address :write address of bar0 mapped area in hex. (default mapping of
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bar0 is SYSRAM1(E0800000). Always program bar size before bar
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address. Kernel might modify bar size and address for alignment, so
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read back bar size and address after writing to cross check.
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bar0_rw_offset :write offset of bar0 for which bar0_data will write value.
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bar0_data :write data to be written at bar0_rw_offset.
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Node programming example
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===========================
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Program all PCIe registers in such a way that when this device is connected
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to the PCIe host, then host sees this device as 1MB RAM.
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#mount -t configfs none /Config
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For nth PCIe Device Controller
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# cd /config/pcie_gadget.n/
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Now you have all the nodes in this directory.
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program vendor id as 0x104a
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# echo 104A >> vendor_id
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program device id as 0xCD80
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# echo CD80 >> device_id
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program BAR0 size as 1MB
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# echo 100000 >> bar0_size
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check for programmed bar0 size
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# cat bar0_size
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Program BAR0 Address as DDR (0x2100000). This is the physical address of
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memory, which is to be made visible to PCIe host. Similarly any other peripheral
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can also be made visible to PCIe host. E.g., if you program base address of UART
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as BAR0 address then when this device will be connected to a host, it will be
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visible as UART.
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# echo 2100000 >> bar0_address
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program interrupt type : INTA
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# echo INTA >> int_type
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go for link up now.
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# echo UP >> link
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It will have to be insured that, once link up is done on gadget, then only host
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is initialized and start to search PCIe devices on its port.
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/*wait till link is up*/
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# cat link
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wait till it returns UP.
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To assert INTA
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# echo 1 >> inta
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To de-assert INTA
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# echo 0 >> inta
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if MSI is to be used as interrupt, program no of msi vector needed (say4)
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# echo 4 >> no_of_msi
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select MSI as interrupt type
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# echo MSI >> int_type
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go for link up now
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# echo UP >> link
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wait till link is up
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# cat link
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An application can repetitively read this node till link is found UP. It can
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sleep between two read.
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wait till msi is enabled
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# cat no_of_msi
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Should return 4 (number of requested MSI vector)
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to send msi vector 2
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# echo 2 >> send_msi
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#cd -
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