275 lines
7 KiB
C
275 lines
7 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2011 John Crispin <john@phrozen.org>
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/export.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <lantiq_soc.h>
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#include <xway_dma.h>
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#define LTQ_DMA_ID 0x08
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#define LTQ_DMA_CTRL 0x10
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#define LTQ_DMA_CPOLL 0x14
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#define LTQ_DMA_CS 0x18
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#define LTQ_DMA_CCTRL 0x1C
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#define LTQ_DMA_CDBA 0x20
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#define LTQ_DMA_CDLEN 0x24
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#define LTQ_DMA_CIS 0x28
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#define LTQ_DMA_CIE 0x2C
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#define LTQ_DMA_PS 0x40
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#define LTQ_DMA_PCTRL 0x44
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#define LTQ_DMA_IRNEN 0xf4
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#define DMA_DESCPT BIT(3) /* descriptor complete irq */
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#define DMA_TX BIT(8) /* TX channel direction */
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#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
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#define DMA_PDEN BIT(6) /* enable packet drop */
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#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
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#define DMA_RESET BIT(0) /* channel on / off bit */
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#define DMA_IRQ_ACK 0x7e /* IRQ status register */
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#define DMA_POLL BIT(31) /* turn on channel polling */
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#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
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#define DMA_2W_BURST BIT(1) /* 2 word burst length */
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#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
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#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
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#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
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#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
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#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
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#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
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ltq_dma_membase + (z))
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static void __iomem *ltq_dma_membase;
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static DEFINE_SPINLOCK(ltq_dma_lock);
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void
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ltq_dma_enable_irq(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
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void
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ltq_dma_disable_irq(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
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void
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ltq_dma_ack_irq(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
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void
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ltq_dma_open(struct ltq_dma_channel *ch)
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{
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unsigned long flag;
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spin_lock_irqsave(<q_dma_lock, flag);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
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ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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spin_unlock_irqrestore(<q_dma_lock, flag);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_open);
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void
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ltq_dma_close(struct ltq_dma_channel *ch)
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{
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unsigned long flag;
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spin_lock_irqsave(<q_dma_lock, flag);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
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spin_unlock_irqrestore(<q_dma_lock, flag);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_close);
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static void
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ltq_dma_alloc(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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ch->desc = 0;
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ch->desc_base = dma_zalloc_coherent(ch->dev,
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LTQ_DESC_NUM * LTQ_DESC_SIZE,
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&ch->phys, GFP_ATOMIC);
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
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ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
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ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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wmb();
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ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
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while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
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;
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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void
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ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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ltq_dma_alloc(ch);
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
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ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
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void
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ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
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{
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unsigned long flags;
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ltq_dma_alloc(ch);
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spin_lock_irqsave(<q_dma_lock, flags);
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ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
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ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
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spin_unlock_irqrestore(<q_dma_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
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void
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ltq_dma_free(struct ltq_dma_channel *ch)
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{
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if (!ch->desc_base)
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return;
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ltq_dma_close(ch);
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dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
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ch->desc_base, ch->phys);
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}
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EXPORT_SYMBOL_GPL(ltq_dma_free);
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void
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ltq_dma_init_port(int p)
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{
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ltq_dma_w32(p, LTQ_DMA_PS);
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switch (p) {
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case DMA_PORT_ETOP:
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/*
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* Tell the DMA engine to swap the endianness of data frames and
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* drop packets if the channel arbitration fails.
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*/
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ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
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LTQ_DMA_PCTRL);
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break;
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case DMA_PORT_DEU:
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ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
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LTQ_DMA_PCTRL);
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break;
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default:
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break;
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}
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}
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EXPORT_SYMBOL_GPL(ltq_dma_init_port);
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static int
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ltq_dma_init(struct platform_device *pdev)
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{
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struct clk *clk;
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struct resource *res;
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unsigned id;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ltq_dma_membase))
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panic("Failed to remap dma resource");
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/* power up and reset the dma engine */
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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panic("Failed to get dma clock");
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clk_enable(clk);
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ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
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/* disable all interrupts */
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ltq_dma_w32(0, LTQ_DMA_IRNEN);
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/* reset/configure each channel */
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for (i = 0; i < DMA_MAX_CHANNEL; i++) {
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ltq_dma_w32(i, LTQ_DMA_CS);
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ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
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ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
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ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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}
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id = ltq_dma_r32(LTQ_DMA_ID);
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dev_info(&pdev->dev,
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"Init done - hw rev: %X, ports: %d, channels: %d\n",
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id & 0x1f, (id >> 16) & 0xf, id >> 20);
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return 0;
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}
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static const struct of_device_id dma_match[] = {
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{ .compatible = "lantiq,dma-xway" },
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{},
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};
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static struct platform_driver dma_driver = {
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.probe = ltq_dma_init,
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.driver = {
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.name = "dma-xway",
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.of_match_table = dma_match,
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},
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};
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int __init
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dma_init(void)
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{
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return platform_driver_register(&dma_driver);
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}
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postcore_initcall(dma_init);
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