195 lines
3.6 KiB
C
195 lines
3.6 KiB
C
/*
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* include/asm-xtensa/asmmacro.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_ASMMACRO_H
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#define _XTENSA_ASMMACRO_H
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#include <variant/core.h>
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/*
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* Some little helpers for loops. Use zero-overhead-loops
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* where applicable and if supported by the processor.
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*
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* __loopi ar, at, size, inc
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* ar register initialized with the start address
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* at scratch register used by macro
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* size size immediate value
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* inc increment
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*
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* __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
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* ar register initialized with the start address
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* as register initialized with the size
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* at scratch register use by macro
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* inc_log2 increment [in log2]
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* mask_log2 mask [in log2]
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* cond true condition (used in loop'cond')
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* ncond false condition (used in b'ncond')
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*
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* __loop as
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* restart loop. 'as' register must not have been modified!
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*
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* __endla ar, as, incr
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* ar start address (modified)
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* as scratch register used by __loops/__loopi macros or
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* end address used by __loopt macro
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* inc increment
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*/
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/*
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* loop for given size as immediate
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*/
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.macro __loopi ar, at, size, incr
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#if XCHAL_HAVE_LOOPS
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movi \at, ((\size + \incr - 1) / (\incr))
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loop \at, 99f
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#else
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addi \at, \ar, \size
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98:
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#endif
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.endm
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/*
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* loop for given size in register
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*/
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.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
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#if XCHAL_HAVE_LOOPS
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.ifgt \incr_log2 - 1
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addi \at, \as, (1 << \incr_log2) - 1
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.ifnc \mask_log2,
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extui \at, \at, \incr_log2, \mask_log2
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.else
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srli \at, \at, \incr_log2
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.endif
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.endif
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loop\cond \at, 99f
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#else
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.ifnc \mask_log2,
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extui \at, \as, \incr_log2, \mask_log2
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.else
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.ifnc \ncond,
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srli \at, \as, \incr_log2
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.endif
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.endif
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.ifnc \ncond,
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b\ncond \at, 99f
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.endif
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.ifnc \mask_log2,
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slli \at, \at, \incr_log2
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add \at, \ar, \at
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.else
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add \at, \ar, \as
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.endif
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#endif
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98:
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.endm
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/*
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* loop from ar to as
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*/
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.macro __loopt ar, as, at, incr_log2
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#if XCHAL_HAVE_LOOPS
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sub \at, \as, \ar
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.ifgt \incr_log2 - 1
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addi \at, \at, (1 << \incr_log2) - 1
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srli \at, \at, \incr_log2
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.endif
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loop \at, 99f
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#else
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98:
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#endif
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.endm
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/*
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* restart loop. registers must be unchanged
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*/
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.macro __loop as
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#if XCHAL_HAVE_LOOPS
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loop \as, 99f
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#else
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98:
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#endif
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.endm
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/*
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* end of loop with no increment of the address.
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*/
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.macro __endl ar, as
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#if !XCHAL_HAVE_LOOPS
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bltu \ar, \as, 98b
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#endif
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99:
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.endm
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/*
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* end of loop with increment of the address.
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*/
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.macro __endla ar, as, incr
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addi \ar, \ar, \incr
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__endl \ar \as
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.endm
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/* Load or store instructions that may cause exceptions use the EX macro. */
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#define EX(handler) \
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.section __ex_table, "a"; \
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.word 97f, handler; \
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.previous \
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97:
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/*
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* Extract unaligned word that is split between two registers w0 and w1
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* into r regardless of machine endianness. SAR must be loaded with the
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* starting bit of the word (see __ssa8).
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*/
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.macro __src_b r, w0, w1
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#ifdef __XTENSA_EB__
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src \r, \w0, \w1
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#else
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src \r, \w1, \w0
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#endif
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.endm
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/*
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* Load 2 lowest address bits of r into SAR for __src_b to extract unaligned
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* word starting at r from two registers loaded from consecutive aligned
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* addresses covering r regardless of machine endianness.
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*
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* r 0 1 2 3
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* LE SAR 0 8 16 24
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* BE SAR 32 24 16 8
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*/
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.macro __ssa8 r
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#ifdef __XTENSA_EB__
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ssa8b \r
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#else
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ssa8l \r
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#endif
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.endm
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#endif /* _XTENSA_ASMMACRO_H */
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