173 lines
3.6 KiB
C
173 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Joey Pan <joey.pan@mediatek.com>
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*/
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#ifndef __DDP_AAL_H__
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#define __DDP_AAL_H__
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#define AAL_HIST_BIN 33 /* [0..32] */
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#define AAL_DRE_POINT_NUM 29
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#define AAL_DRE30_GAIN_REGISTER_NUM (544)
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#define AAL_DRE30_HIST_REGISTER_NUM (768)
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#define AAL_SERVICE_FORCE_UPDATE 0x1
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/* Custom "wide" pointer type for 64-bit compatibility. */
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/* Always cast from uint32_t*. */
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/* typedef unsigned long long aal_u32_ptr_t; */
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#define aal_u32_handle_t unsigned long long
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#define AAL_U32_PTR(x) ((unsigned int *)(unsigned long)x)
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enum disp_aal_id_t {
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DISP_AAL0 = 0,
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DISP_AAL1,
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DISP_AAL_TOTAL
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};
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enum AAL_ESS_UD_MODE {
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CONFIG_BY_CUSTOM_LIB = 0,
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CONFIG_TO_LCD = 1,
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CONFIG_TO_AMOLED = 2
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};
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enum AAL_DRE_MODE {
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DRE_EN_BY_CUSTOM_LIB = 0xFFFF,
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DRE_OFF = 0,
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DRE_ON = 1
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};
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enum AAL_ESS_MODE {
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ESS_EN_BY_CUSTOM_LIB = 0xFFFF,
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ESS_OFF = 0,
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ESS_ON = 1
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};
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enum AAL_ESS_LEVEL {
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ESS_LEVEL_BY_CUSTOM_LIB = 0xFFFF
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};
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#define AAL_CONTROL_CMD(ID, CONTROL) (ID << 16 | CONTROL)
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struct DISP_AAL_INITREG {
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/* DRE */
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int dre_map_bypass;
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/* ESS */
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int cabc_gainlmt[33];
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/* DRE 3.0 Reg. */
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int dre_s_lower;
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int dre_s_upper;
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int dre_y_lower;
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int dre_y_upper;
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int dre_h_lower;
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int dre_h_upper;
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int dre_h_slope;
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int dre_s_slope;
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int dre_y_slope;
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int dre_x_alpha_base;
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int dre_x_alpha_shift_bit;
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int dre_y_alpha_base;
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int dre_y_alpha_shift_bit;
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int act_win_x_end;
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int dre_blk_x_num;
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int dre_blk_y_num;
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int dre_blk_height;
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int dre_blk_width;
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int dre_blk_area;
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int dre_blk_area_min;
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int hist_bin_type;
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int dre_flat_length_slope;
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int dre_flat_length_th;
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int act_win_y_start;
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int act_win_y_end;
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int blk_num_x_start;
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int blk_num_x_end;
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int blk_cnt_x_start;
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int blk_cnt_x_end;
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int blk_num_y_start;
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int blk_num_y_end;
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int blk_cnt_y_start;
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int blk_cnt_y_end;
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int last_tile_x_flag;
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int last_tile_y_flag;
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};
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struct DISP_DRE30_INIT {
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/* DRE 3.0 SW */
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aal_u32_handle_t dre30_hist_addr;
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};
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struct DISP_AAL_DISPLAY_SIZE {
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int width;
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int height;
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};
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struct DISP_DRE30_HIST {
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unsigned int dre_hist[AAL_DRE30_HIST_REGISTER_NUM];
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int dre_blk_x_num;
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int dre_blk_y_num;
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};
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struct DISP_AAL_HIST {
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unsigned int serviceFlags;
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int backlight;
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int colorHist;
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unsigned int maxHist[AAL_HIST_BIN];
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int requestPartial;
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aal_u32_handle_t dre30_hist;
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unsigned int panel_type;
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int essStrengthIndex;
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int ess_enable;
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int dre_enable;
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unsigned int yHist[AAL_HIST_BIN];
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};
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struct DISP_AAL_HIST_MODULE {
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int colorHist;
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unsigned int maxHist[AAL_HIST_BIN];
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unsigned int count;
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};
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enum DISP_AAL_REFRESH_LATENCY {
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AAL_REFRESH_17MS = 17,
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AAL_REFRESH_33MS = 33
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};
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struct DISP_DRE30_PARAM {
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unsigned int dre30_gain[AAL_DRE30_GAIN_REGISTER_NUM];
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};
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struct DISP_AAL_PARAM {
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int DREGainFltStatus[AAL_DRE_POINT_NUM];
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int cabc_fltgain_force; /* 10-bit ; [0,1023] */
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int cabc_gainlmt[33];
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int FinalBacklight; /* 10-bit ; [0,1023] */
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int allowPartial;
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int refreshLatency; /* DISP_AAL_REFRESH_LATENCY */
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aal_u32_handle_t dre30_gain;
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};
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extern struct cust_mt65xx_led *pled_dtsi;
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void disp_aal_on_end_of_frame(void);
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void disp_aal_on_end_of_frame_by_module(enum disp_aal_id_t id);
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void disp_aal_on_start_of_frame(enum disp_aal_id_t id);
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extern int aal_dbg_en;
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void aal_test(const char *cmd, char *debug_output);
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bool disp_aal_is_support(void);
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int aal_is_partial_support(void);
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int aal_request_partial_support(int partial);
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void disp_aal_notify_backlight_changed(int bl_1024);
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void disp_aal_set_lcm_type(unsigned int panel_type);
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void disp_aal_set_ess_level(int level);
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void disp_aal_set_ess_en(int enable);
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void disp_aal_set_dre_en(int enable);
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#endif
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