208 lines
6 KiB
C
208 lines
6 KiB
C
/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/netdevice.h>
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#include "altera_utils.h"
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#include "altera_tse.h"
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#include "altera_msgdmahw.h"
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#include "altera_msgdma.h"
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/* No initialization work to do for MSGDMA */
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int msgdma_initialize(struct altera_tse_private *priv)
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{
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return 0;
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}
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void msgdma_uninitialize(struct altera_tse_private *priv)
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{
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}
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void msgdma_start_rxdma(struct altera_tse_private *priv)
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{
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}
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void msgdma_reset(struct altera_tse_private *priv)
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{
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int counter;
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/* Reset Rx mSGDMA */
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csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
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msgdma_csroffs(status));
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csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
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msgdma_csroffs(control));
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counter = 0;
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while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
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if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
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MSGDMA_CSR_STAT_RESETTING))
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break;
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udelay(1);
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}
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if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
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netif_warn(priv, drv, priv->dev,
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"TSE Rx mSGDMA resetting bit never cleared!\n");
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/* clear all status bits */
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csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
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/* Reset Tx mSGDMA */
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csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
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msgdma_csroffs(status));
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csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
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msgdma_csroffs(control));
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counter = 0;
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while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
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if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
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MSGDMA_CSR_STAT_RESETTING))
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break;
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udelay(1);
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}
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if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
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netif_warn(priv, drv, priv->dev,
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"TSE Tx mSGDMA resetting bit never cleared!\n");
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/* clear all status bits */
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csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
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}
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void msgdma_disable_rxirq(struct altera_tse_private *priv)
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{
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tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
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MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_enable_rxirq(struct altera_tse_private *priv)
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{
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tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
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MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_disable_txirq(struct altera_tse_private *priv)
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{
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tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
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MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_enable_txirq(struct altera_tse_private *priv)
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{
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tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
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MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_clear_rxirq(struct altera_tse_private *priv)
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{
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csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
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}
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void msgdma_clear_txirq(struct altera_tse_private *priv)
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{
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csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
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}
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/* return 0 to indicate transmit is pending */
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int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
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msgdma_descroffs(read_addr_lo));
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csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
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msgdma_descroffs(read_addr_hi));
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csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
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csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
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csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
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csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
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csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
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msgdma_descroffs(stride));
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csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
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msgdma_descroffs(control));
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return 0;
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}
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u32 msgdma_tx_completions(struct altera_tse_private *priv)
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{
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u32 ready = 0;
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u32 inuse;
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u32 status;
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/* Get number of sent descriptors */
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inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
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& 0xffff;
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if (inuse) { /* Tx FIFO is not empty */
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ready = max_t(int,
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priv->tx_prod - priv->tx_cons - inuse - 1, 0);
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} else {
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/* Check for buffered last packet */
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status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
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if (status & MSGDMA_CSR_STAT_BUSY)
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ready = priv->tx_prod - priv->tx_cons - 1;
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else
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ready = priv->tx_prod - priv->tx_cons;
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}
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return ready;
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}
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/* Put buffer to the mSGDMA RX FIFO
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*/
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void msgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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u32 len = priv->rx_dma_buf_sz;
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dma_addr_t dma_addr = rxbuffer->dma_addr;
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u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
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| MSGDMA_DESC_CTL_END_ON_LEN
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| MSGDMA_DESC_CTL_TR_COMP_IRQ
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| MSGDMA_DESC_CTL_EARLY_IRQ
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| MSGDMA_DESC_CTL_TR_ERR_IRQ
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| MSGDMA_DESC_CTL_GO);
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csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
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csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
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csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
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msgdma_descroffs(write_addr_lo));
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csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
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msgdma_descroffs(write_addr_hi));
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csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
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csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
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csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
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csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
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}
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/* status is returned on upper 16 bits,
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* length is returned in lower 16 bits
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*/
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u32 msgdma_rx_status(struct altera_tse_private *priv)
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{
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u32 rxstatus = 0;
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u32 pktlength;
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u32 pktstatus;
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if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
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& 0xffff) {
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pktlength = csrrd32(priv->rx_dma_resp,
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msgdma_respoffs(bytes_transferred));
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pktstatus = csrrd32(priv->rx_dma_resp,
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msgdma_respoffs(status));
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rxstatus = pktstatus;
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rxstatus = rxstatus << 16;
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rxstatus |= (pktlength & 0xffff);
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}
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return rxstatus;
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}
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