105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Houlong Wei <houlong.wei@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_GCE_MT2712_H
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#define _DT_BINDINGS_GCE_MT2712_H
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/* GCE HW thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_HIGHEST 1
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/* GCE SUBSYS */
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1403XXXX 23
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/* GCE HW EVENT */
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#define CMDQ_EVENT_MDP_RDMA0_SOF 0
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#define CMDQ_EVENT_MDP_RDMA1_SOF 1
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#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
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#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
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#define CMDQ_EVENT_MDP_WDMA_SOF 7
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#define CMDQ_EVENT_MDP_WROT0_SOF 8
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#define CMDQ_EVENT_MDP_WROT1_SOF 9
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#define CMDQ_EVENT_MDP_CROP_SOF 10
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#define CMDQ_EVENT_DISP_OVL0_SOF 11
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#define CMDQ_EVENT_DISP_OVL1_SOF 12
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#define CMDQ_EVENT_DISP_RDMA0_SOF 13
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#define CMDQ_EVENT_DISP_RDMA1_SOF 14
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#define CMDQ_EVENT_DISP_RDMA2_SOF 15
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#define CMDQ_EVENT_DISP_WDMA0_SOF 16
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#define CMDQ_EVENT_DISP_WDMA1_SOF 17
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#define CMDQ_EVENT_DISP_COLOR0_SOF 18
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#define CMDQ_EVENT_DISP_COLOR1_SOF 19
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#define CMDQ_EVENT_DISP_AAL0_SOF 20
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#define CMDQ_EVENT_DISP_GAMMA_SOF 21
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#define CMDQ_EVENT_DISP_UFOE_SOF 22
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#define CMDQ_EVENT_DISP_PWM0_SOF 23
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#define CMDQ_EVENT_DISP_PWM1_SOF 24
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#define CMDQ_EVENT_DISP_OD0_SOF 25
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#define CMDQ_EVENT_MDP_RDMA2_SOF 26
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#define CMDQ_EVENT_MDP_RDMA3_SOF 27
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#define CMDQ_EVENT_MDP_TDSHP2_SOF 28
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#define CMDQ_EVENT_MDP_WROT2_SOF 29
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#define CMDQ_EVENT_DISP_OVL2_SOF 30
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#define CMDQ_EVENT_DISP_WDMA2_SOF 31
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#define CMDQ_EVENT_DISP_COLOR2_SOF 32
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#define CMDQ_EVENT_DISP_AAL1_SOF 33
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#define CMDQ_EVENT_DISP_OD1_SOF 34
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#define CMDQ_EVENT_MDP_RDMA0_EOF 37
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#define CMDQ_EVENT_MDP_RDMA1_EOF 38
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#define CMDQ_EVENT_MDP_RSZ0_EOF 39
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#define CMDQ_EVENT_MDP_RSZ1_EOF 40
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#define CMDQ_EVENT_MDP_RSZ2_EOF 41
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#define CMDQ_EVENT_MDP_TDSHP0_EOF 42
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#define CMDQ_EVENT_MDP_TDSHP1_EOF 43
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#define CMDQ_EVENT_MDP_WDMA_EOF 44
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#define CMDQ_EVENT_MDP_WROT0_W_EOF 45
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#define CMDQ_EVENT_MDP_WROT0_R_EOF 46
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#define CMDQ_EVENT_MDP_WROT1_W_EOF 47
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#define CMDQ_EVENT_MDP_WROT1_R_EOF 48
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#define CMDQ_EVENT_MDP_CROP_EOF 49
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#define CMDQ_EVENT_DISP_OVL0_EOF 50
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#define CMDQ_EVENT_DISP_OVL1_EOF 51
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#define CMDQ_EVENT_DISP_RDMA0_EOF 52
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#define CMDQ_EVENT_DISP_RDMA1_EOF 53
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#define CMDQ_EVENT_DISP_RDMA2_EOF 54
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#define CMDQ_EVENT_DISP_WDMA0_EOF 55
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#define CMDQ_EVENT_DISP_WDMA1_EOF 56
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#define CMDQ_EVENT_DISP_COLOR0_EOF 57
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#define CMDQ_EVENT_DISP_COLOR1_EOF 58
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#define CMDQ_EVENT_DISP_AAL0_EOF 59
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#define CMDQ_EVENT_DISP_GAMMA_EOF 60
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#define CMDQ_EVENT_DISP_UFOE_EOF 61
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#define CMDQ_EVENT_DISP_DPI0_EOF 62
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#define CMDQ_EVENT_DISP_DPI1_EOF 63
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#define CMDQ_EVENT_MDP_RDMA2_EOF 64
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#define CMDQ_EVENT_MDP_RDMA3_EOF 65
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#define CMDQ_EVENT_MDP_WROT2_W_EOF 66
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#define CMDQ_EVENT_MDP_WROT2_R_EOF 67
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#define CMDQ_EVENT_MDP_TDSHP2_EOF 68
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#define CMDQ_EVENT_DISP_OVL2_EOF 69
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#define CMDQ_EVENT_DISP_WDMA2_EOF 70
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#define CMDQ_EVENT_DISP_COLOR2_EOF 71
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#define CMDQ_EVENT_DISP_AAL1_EOF 72
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#define CMDQ_EVENT_DISP_OD0_EOF 73
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#define CMDQ_EVENT_DISP_OD1_EOF 74
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#define CMDQ_EVENT_DISP_DSI0_EOF 75
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#define CMDQ_EVENT_DISP_DSI1_EOF 76
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#define CMDQ_EVENT_DISP_DSI2_EOF 77
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#define CMDQ_EVENT_DISP_DSI3_EOF 78
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#define CMDQ_EVENT_MUTEX0_STREAM_EOF 79
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#define CMDQ_EVENT_MUTEX1_STREAM_EOF 80
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#define CMDQ_EVENT_MUTEX2_STREAM_EOF 81
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#define CMDQ_EVENT_MUTEX3_STREAM_EOF 82
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#define CMDQ_EVENT_MUTEX4_STREAM_EOF 83
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#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 89
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#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 90
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#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 91
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#endif
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