331 lines
8.2 KiB
ArmAsm
331 lines
8.2 KiB
ArmAsm
/*
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* Cache maintenance
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/asm-uaccess.h>
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/*
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* __flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: x0-x7, x9-x11
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*/
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__flush_dcache_all:
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dmb sy // ensure ordering with previous memory accesses
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mrs x0, clidr_el1 // read clidr
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and x3, x0, #0x7000000 // extract loc from clidr
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lsr x3, x3, #23 // left align loc bit field
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cbz x3, finished // if loc is 0, then no need to clean
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mov x10, #0 // start clean at cache level 0
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask of the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt skip // skip if no cache, or just i-cache
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save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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restore_irqs x9
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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mov x4, #0x3ff
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and x4, x4, x1, lsr #3 // find maximum number on the way size
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clz w5, w4 // find bit position of way size increment
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mov x7, #0x7fff
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and x7, x7, x1, lsr #13 // extract max number of the index size
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loop2:
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mov x9, x4 // create working copy of max way size
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loop3:
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lsl x6, x9, x5
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orr x11, x10, x6 // factor way and cache number into x11
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lsl x6, x7, x2
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orr x11, x11, x6 // factor index number into x11
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dc cisw, x11 // clean & invalidate by set/way
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subs x9, x9, #1 // decrement the way
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b.ge loop3
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subs x7, x7, #1 // decrement the index
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b.ge loop2
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skip:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt loop1
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finished:
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mov x10, #0 // swith back to cache level 0
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msr csselr_el1, x10 // select current cache level in csselr
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dsb sy
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isb
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ret
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ENDPROC(__flush_dcache_all)
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/*
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* flush_cache_all()
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*
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* Flush the entire cache system. The data cache flush is now achieved
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* using atomic clean / invalidates working outwards from L1 cache. This
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* is done using Set/Way based cache maintenance instructions. The
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* instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*/
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ENTRY(flush_cache_all)
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mov x12, lr
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bl __flush_dcache_all
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mov x0, #0
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ic ialluis // I+BTB cache invalidate
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ret x12
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ENDPROC(flush_cache_all)
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/*
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* flush_icache_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__flush_icache_range)
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/* FALLTHROUGH */
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/*
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* __flush_cache_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(__flush_cache_user_range)
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uaccess_ttbr0_enable x2, x3, x4
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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b 7f
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alternative_else_nop_endif
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x4, x0, x3
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1:
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user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
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add x4, x4, x2
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cmp x4, x1
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b.lo 1b
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dsb ish
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7:
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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b 8f
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3, 9f
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8: mov x0, #0
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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9:
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mov x0, #-EFAULT
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b 1b
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ENDPROC(__flush_icache_range)
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ENDPROC(__flush_cache_user_range)
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/*
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* invalidate_icache_range(start,end)
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*
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* Ensure that the I cache is invalid within specified region.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(invalidate_icache_range)
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alternative_if ARM64_HAS_CACHE_DIC
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mov x0, xzr
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isb
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ret
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alternative_else_nop_endif
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uaccess_ttbr0_enable x2, x3, x4
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invalidate_icache_by_line x0, x1, x2, x3, 2f
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mov x0, xzr
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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2:
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mov x0, #-EFAULT
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b 1b
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ENDPROC(invalidate_icache_range)
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/*
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* __flush_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned and invalidated to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__flush_dcache_area)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__flush_dcache_area)
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/*
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* __clean_dcache_area_pou(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoU.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_pou)
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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ret
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alternative_else_nop_endif
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dcache_by_line_op cvau, ish, x0, x1, x2, x3
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ret
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ENDPROC(__clean_dcache_area_pou)
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/*
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* __inval_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are invalidated. Any partial lines at the ends of the interval are
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* also cleaned to PoC to prevent data loss.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__inval_dcache_area)
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/* FALLTHROUGH */
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/*
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* __dma_inv_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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ENTRY(__dma_inv_area)
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add x1, x1, x0
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dcache_line_size x2, x3
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sub x3, x2, #1
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tst x1, x3 // end cache line aligned?
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bic x1, x1, x3
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b.eq 1f
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dc civac, x1 // clean & invalidate D / U line
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1: tst x0, x3 // start cache line aligned?
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bic x0, x0, x3
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b.eq 2f
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dc civac, x0 // clean & invalidate D / U line
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b 3f
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2: dc ivac, x0 // invalidate D / U line
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3: add x0, x0, x2
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cmp x0, x1
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b.lo 2b
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dsb sy
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ret
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ENDPIPROC(__inval_dcache_area)
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ENDPROC(__dma_inv_area)
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/*
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* __clean_dcache_area_poc(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_poc)
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/* FALLTHROUGH */
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/*
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* __dma_clean_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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ENTRY(__dma_clean_area)
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dcache_by_line_op cvac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__clean_dcache_area_poc)
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ENDPROC(__dma_clean_area)
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/*
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* __clean_dcache_area_pop(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoP.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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ENTRY(__clean_dcache_area_pop)
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alternative_if_not ARM64_HAS_DCPOP
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b __clean_dcache_area_poc
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alternative_else_nop_endif
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dcache_by_line_op cvap, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__clean_dcache_area_pop)
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/*
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* __dma_flush_area(start, size)
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*
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* clean & invalidate D / U line
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*
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* - start - virtual start address of region
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* - size - size in question
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*/
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ENTRY(__dma_flush_area)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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ENDPIPROC(__dma_flush_area)
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/*
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* __dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(__dma_map_area)
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cmp w2, #DMA_FROM_DEVICE
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b.eq __dma_inv_area
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b __dma_clean_area
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ENDPIPROC(__dma_map_area)
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/*
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* __dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(__dma_unmap_area)
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cmp w2, #DMA_TO_DEVICE
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b.ne __dma_inv_area
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ret
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ENDPIPROC(__dma_unmap_area)
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