263 lines
7.4 KiB
C
263 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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/*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This struct defines the way the registers are stored on the
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* kernel stack during a system call or other kernel entry.
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*
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* this should only contain volatile regs
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* since we can keep non-volatile in the thread_struct
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* should set this up when only volatiles are saved
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* by intr code.
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*
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* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
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* that the overall structure is a multiple of 16 bytes in length.
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*
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* Note that the offsets of the fields in this struct correspond with
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* the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _UAPI_ASM_POWERPC_PTRACE_H
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#define _UAPI_ASM_POWERPC_PTRACE_H
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#include <linux/types.h>
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#ifndef __ASSEMBLY__
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struct pt_regs {
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unsigned long gpr[32];
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unsigned long nip;
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unsigned long msr;
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unsigned long orig_gpr3; /* Used for restarting system calls */
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unsigned long ctr;
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unsigned long link;
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unsigned long xer;
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unsigned long ccr;
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#ifdef __powerpc64__
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unsigned long softe; /* Soft enabled/disabled */
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#else
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unsigned long mq; /* 601 only (not used at present) */
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/* Used on APUS to hold IPL value. */
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#endif
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unsigned long trap; /* Reason for being here */
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/* N.B. for critical exceptions on 4xx, the dar and dsisr
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fields are overloaded to hold srr0 and srr1. */
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unsigned long dar; /* Fault registers */
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unsigned long dsisr; /* on 4xx/Book-E used for ESR */
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unsigned long result; /* Result of a system call */
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};
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#endif /* __ASSEMBLY__ */
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/*
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* Offsets used by 'ptrace' system call interface.
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* These can't be changed without breaking binary compatibility
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* with MkLinux, etc.
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*/
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#define PT_R0 0
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#define PT_R1 1
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#define PT_R2 2
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#define PT_R3 3
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#define PT_R4 4
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#define PT_R5 5
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#define PT_R6 6
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#define PT_R7 7
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#define PT_R8 8
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#define PT_R9 9
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#define PT_R10 10
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#define PT_R11 11
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#define PT_R12 12
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#define PT_R13 13
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#define PT_R14 14
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#define PT_R15 15
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#define PT_R16 16
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#define PT_R17 17
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#define PT_R18 18
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#define PT_R19 19
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#define PT_R20 20
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#define PT_R21 21
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#define PT_R22 22
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#define PT_R23 23
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#define PT_R24 24
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#define PT_R25 25
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#define PT_R26 26
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#define PT_R27 27
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#define PT_R28 28
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#define PT_R29 29
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#define PT_R30 30
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#define PT_R31 31
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#define PT_NIP 32
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#define PT_MSR 33
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#define PT_ORIG_R3 34
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#define PT_CTR 35
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#define PT_LNK 36
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#define PT_XER 37
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#define PT_CCR 38
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#ifndef __powerpc64__
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#define PT_MQ 39
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#else
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#define PT_SOFTE 39
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#endif
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#define PT_TRAP 40
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#define PT_DAR 41
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#define PT_DSISR 42
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#define PT_RESULT 43
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#define PT_DSCR 44
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#define PT_REGS_COUNT 44
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#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
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#ifndef __powerpc64__
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#define PT_FPR31 (PT_FPR0 + 2*31)
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#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
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#else /* __powerpc64__ */
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#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
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#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
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#define PT_VSCR (PT_VR0 + 32*2 + 1)
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#define PT_VRSAVE (PT_VR0 + 33*2)
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/*
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* Only store first 32 VSRs here. The second 32 VSRs in VR0-31
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*/
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#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
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#define PT_VSR31 (PT_VSR0 + 2*31)
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#endif /* __powerpc64__ */
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/*
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* Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
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* The transfer totals 34 quadword. Quadwords 0-31 contain the
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* corresponding vector registers. Quadword 32 contains the vscr as the
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* last word (offset 12) within that quadword. Quadword 33 contains the
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* vrsave as the first word (offset 0) within the quadword.
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*
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* This definition of the VMX state is compatible with the current PPC32
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* ptrace interface. This allows signal handling and ptrace to use the same
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* structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*/
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#define PTRACE_GETVRREGS 0x12
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#define PTRACE_SETVRREGS 0x13
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/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
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* spefscr, in one go */
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#define PTRACE_GETEVRREGS 0x14
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#define PTRACE_SETEVRREGS 0x15
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/* Get the first 32 128bit VSX registers */
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#define PTRACE_GETVSRREGS 0x1b
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#define PTRACE_SETVSRREGS 0x1c
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/*
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* Get or set a debug register. The first 16 are DABR registers and the
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* second 16 are IABR registers.
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*/
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#define PTRACE_GET_DEBUGREG 0x19
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#define PTRACE_SET_DEBUGREG 0x1a
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/* (new) PTRACE requests using the same numbers as x86 and the same
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* argument ordering. Additionally, they support more registers too
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*/
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#define PTRACE_GETREGS 0xc
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#define PTRACE_SETREGS 0xd
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#define PTRACE_GETFPREGS 0xe
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#define PTRACE_SETFPREGS 0xf
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#define PTRACE_GETREGS64 0x16
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#define PTRACE_SETREGS64 0x17
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/* Calls to trace a 64bit program from a 32bit program */
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#define PPC_PTRACE_PEEKTEXT_3264 0x95
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#define PPC_PTRACE_PEEKDATA_3264 0x94
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#define PPC_PTRACE_POKETEXT_3264 0x93
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#define PPC_PTRACE_POKEDATA_3264 0x92
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#define PPC_PTRACE_PEEKUSR_3264 0x91
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#define PPC_PTRACE_POKEUSR_3264 0x90
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#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
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#define PPC_PTRACE_GETHWDBGINFO 0x89
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#define PPC_PTRACE_SETHWDEBUG 0x88
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#define PPC_PTRACE_DELHWDEBUG 0x87
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#ifndef __ASSEMBLY__
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struct ppc_debug_info {
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__u32 version; /* Only version 1 exists to date */
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__u32 num_instruction_bps;
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__u32 num_data_bps;
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__u32 num_condition_regs;
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__u32 data_bp_alignment;
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__u32 sizeof_condition; /* size of the DVC register */
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__u64 features;
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};
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#endif /* __ASSEMBLY__ */
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/*
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* features will have bits indication whether there is support for:
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*/
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#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
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#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
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#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
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#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
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#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010
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#ifndef __ASSEMBLY__
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struct ppc_hw_breakpoint {
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__u32 version; /* currently, version must be 1 */
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__u32 trigger_type; /* only some combinations allowed */
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__u32 addr_mode; /* address match mode */
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__u32 condition_mode; /* break/watchpoint condition flags */
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__u64 addr; /* break/watchpoint address */
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__u64 addr2; /* range end or mask */
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__u64 condition_value; /* contents of the DVC register */
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};
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#endif /* __ASSEMBLY__ */
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/*
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* Trigger Type
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*/
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#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
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#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
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#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
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#define PPC_BREAKPOINT_TRIGGER_RW \
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(PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
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/*
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* Address Mode
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*/
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#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
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#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
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#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
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#define PPC_BREAKPOINT_MODE_MASK 0x00000003
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/*
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* Condition Mode
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*/
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#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
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#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
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#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
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#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
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#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
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#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
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#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
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#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
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#define PPC_BREAKPOINT_CONDITION_BE(n) \
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(1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
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#endif /* _UAPI_ASM_POWERPC_PTRACE_H */
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