222 lines
5.9 KiB
C
222 lines
5.9 KiB
C
/*
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* IBM/AMCC PPC4xx SoC setup code
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*
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* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003 - 2006 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#include <asm/reg.h>
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static u32 dcrbase_l2c;
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/*
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* L2-cache
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*/
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/* Issue L2C diagnostic command */
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static inline u32 l2c_diag(u32 addr)
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{
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
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while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
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;
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return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
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}
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static irqreturn_t l2c_error_handler(int irq, void *dev)
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{
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u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
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if (sr & L2C_SR_CPE) {
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/* Read cache trapped address */
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u32 addr = l2c_diag(0x42000000);
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printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
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addr);
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}
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if (sr & L2C_SR_TPE) {
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/* Read tag trapped address */
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u32 addr = l2c_diag(0x82000000) >> 16;
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printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
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addr);
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}
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/* Clear parity errors */
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if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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} else {
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printk(KERN_EMERG "L2C: LRU error\n");
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}
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return IRQ_HANDLED;
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}
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static int __init ppc4xx_l2c_probe(void)
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{
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struct device_node *np;
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u32 r;
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unsigned long flags;
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int irq;
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const u32 *dcrreg;
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u32 dcrbase_isram;
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int len;
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const u32 *prop;
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u32 l2_size;
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np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
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if (!np)
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return 0;
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/* Get l2 cache size */
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prop = of_get_property(np, "cache-size", NULL);
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if (prop == NULL) {
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printk(KERN_ERR "%pOF: Can't get cache-size!\n", np);
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of_node_put(np);
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return -ENODEV;
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}
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l2_size = prop[0];
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/* Map DCRs */
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dcrreg = of_get_property(np, "dcr-reg", &len);
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if (!dcrreg || (len != 4 * sizeof(u32))) {
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printk(KERN_ERR "%pOF: Can't get DCR register base !", np);
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of_node_put(np);
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return -ENODEV;
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}
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dcrbase_isram = dcrreg[0];
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dcrbase_l2c = dcrreg[2];
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/* Get and map irq number from device tree */
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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printk(KERN_ERR "irq_of_parse_and_map failed\n");
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of_node_put(np);
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return -ENODEV;
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}
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/* Install error handler */
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if (request_irq(irq, l2c_error_handler, 0, "L2C", 0) < 0) {
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printk(KERN_ERR "Cannot install L2C error handler"
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", cache is not enabled\n");
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of_node_put(np);
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return -ENODEV;
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}
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local_irq_save(flags);
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asm volatile ("sync" ::: "memory");
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/* Disable SRAM */
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mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
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mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
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/* Enable L2_MODE without ICU/DCU */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
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~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
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r |= L2C_CFG_L2M | L2C_CFG_SS_256;
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mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
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/* Hardware Clear Command */
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
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while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
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;
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/* Clear Cache Parity and Tag Errors */
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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/* Enable 64G snoop region starting at 0 */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
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~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
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~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
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asm volatile ("sync" ::: "memory");
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/* Enable ICU/DCU ports */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
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r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
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| L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
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r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
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| L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
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/* Check for 460EX/GT special handling */
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if (of_device_is_compatible(np, "ibm,l2-cache-460ex") ||
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of_device_is_compatible(np, "ibm,l2-cache-460gt"))
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r |= L2C_CFG_RDBW;
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mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
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asm volatile ("sync; isync" ::: "memory");
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local_irq_restore(flags);
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printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
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of_node_put(np);
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return 0;
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}
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arch_initcall(ppc4xx_l2c_probe);
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/*
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* Apply a system reset. Alternatively a board specific value may be
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* provided via the "reset-type" property in the cpu node.
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*/
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void ppc4xx_reset_system(char *cmd)
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{
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struct device_node *np;
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u32 reset_type = DBCR0_RST_SYSTEM;
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const u32 *prop;
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np = of_find_node_by_type(NULL, "cpu");
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if (np) {
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prop = of_get_property(np, "reset-type", NULL);
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/*
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* Check if property exists and if it is in range:
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* 1 - PPC4xx core reset
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* 2 - PPC4xx chip reset
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* 3 - PPC4xx system reset (default)
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*/
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if ((prop) && ((prop[0] >= 1) && (prop[0] <= 3)))
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reset_type = prop[0] << 28;
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}
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mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type);
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while (1)
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; /* Just in case the reset doesn't work */
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}
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