528 lines
13 KiB
C
528 lines
13 KiB
C
/*
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* linux/arch/unicore32/mm/alignment.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* TODO:
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* FPU ldm/stm not handling
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*/
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/sched/debug.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/unaligned.h>
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#include "mm.h"
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#define CODING_BITS(i) (i & 0xe0000120)
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#define LDST_P_BIT(i) (i & (1 << 28)) /* Preindex */
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#define LDST_U_BIT(i) (i & (1 << 27)) /* Add offset */
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#define LDST_W_BIT(i) (i & (1 << 25)) /* Writeback */
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#define LDST_L_BIT(i) (i & (1 << 24)) /* Load */
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#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 27)) == 0)
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#define LDSTH_I_BIT(i) (i & (1 << 26)) /* half-word immed */
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#define LDM_S_BIT(i) (i & (1 << 26)) /* write ASR from BSR */
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#define LDM_H_BIT(i) (i & (1 << 6)) /* select r0-r15 or r16-r31 */
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#define RN_BITS(i) ((i >> 19) & 31) /* Rn */
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#define RD_BITS(i) ((i >> 14) & 31) /* Rd */
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#define RM_BITS(i) (i & 31) /* Rm */
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#define REGMASK_BITS(i) (((i & 0x7fe00) >> 3) | (i & 0x3f))
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#define OFFSET_BITS(i) (i & 0x03fff)
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#define SHIFT_BITS(i) ((i >> 9) & 0x1f)
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#define SHIFT_TYPE(i) (i & 0xc0)
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#define SHIFT_LSL 0x00
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#define SHIFT_LSR 0x40
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#define SHIFT_ASR 0x80
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#define SHIFT_RORRRX 0xc0
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union offset_union {
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unsigned long un;
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signed long sn;
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};
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#define TYPE_ERROR 0
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#define TYPE_FAULT 1
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#define TYPE_LDST 2
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#define TYPE_DONE 3
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#define TYPE_SWAP 4
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#define TYPE_COLS 5 /* Coprocessor load/store */
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#define get8_unaligned_check(val, addr, err) \
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__asm__( \
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"1: ldb.u %1, [%2], #1\n" \
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"2:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"3: mov %0, #1\n" \
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" b 2b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 3b\n" \
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" .popsection\n" \
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: "=r" (err), "=&r" (val), "=r" (addr) \
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: "0" (err), "2" (addr))
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#define get8t_unaligned_check(val, addr, err) \
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__asm__( \
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"1: ldb.u %1, [%2], #1\n" \
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"2:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"3: mov %0, #1\n" \
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" b 2b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 3b\n" \
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" .popsection\n" \
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: "=r" (err), "=&r" (val), "=r" (addr) \
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: "0" (err), "2" (addr))
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#define get16_unaligned_check(val, addr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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get8_unaligned_check(val, a, err); \
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get8_unaligned_check(v, a, err); \
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val |= v << 8; \
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if (err) \
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goto fault; \
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} while (0)
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#define put16_unaligned_check(val, addr) \
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( \
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"1: stb.u %1, [%2], #1\n" \
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" mov %1, %1 >> #8\n" \
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"2: stb.u %1, [%2]\n" \
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"3:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %0, #1\n" \
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" b 3b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 4b\n" \
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" .long 2b, 4b\n" \
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" .popsection\n" \
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: "=r" (err), "=&r" (v), "=&r" (a) \
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: "0" (err), "1" (v), "2" (a)); \
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if (err) \
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goto fault; \
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} while (0)
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#define __put32_unaligned_check(ins, val, addr) \
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( \
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"1: "ins" %1, [%2], #1\n" \
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" mov %1, %1 >> #8\n" \
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"2: "ins" %1, [%2], #1\n" \
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" mov %1, %1 >> #8\n" \
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"3: "ins" %1, [%2], #1\n" \
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" mov %1, %1 >> #8\n" \
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"4: "ins" %1, [%2]\n" \
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"5:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"6: mov %0, #1\n" \
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" b 5b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 6b\n" \
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" .long 2b, 6b\n" \
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" .long 3b, 6b\n" \
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" .long 4b, 6b\n" \
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" .popsection\n" \
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: "=r" (err), "=&r" (v), "=&r" (a) \
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: "0" (err), "1" (v), "2" (a)); \
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if (err) \
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goto fault; \
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} while (0)
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#define get32_unaligned_check(val, addr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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get8_unaligned_check(val, a, err); \
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get8_unaligned_check(v, a, err); \
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val |= v << 8; \
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get8_unaligned_check(v, a, err); \
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val |= v << 16; \
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get8_unaligned_check(v, a, err); \
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val |= v << 24; \
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if (err) \
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goto fault; \
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} while (0)
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#define put32_unaligned_check(val, addr) \
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__put32_unaligned_check("stb.u", val, addr)
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#define get32t_unaligned_check(val, addr) \
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do { \
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unsigned int err = 0, v, a = addr; \
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get8t_unaligned_check(val, a, err); \
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get8t_unaligned_check(v, a, err); \
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val |= v << 8; \
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get8t_unaligned_check(v, a, err); \
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val |= v << 16; \
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get8t_unaligned_check(v, a, err); \
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val |= v << 24; \
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if (err) \
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goto fault; \
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} while (0)
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#define put32t_unaligned_check(val, addr) \
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__put32_unaligned_check("stb.u", val, addr)
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static void
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do_alignment_finish_ldst(unsigned long addr, unsigned long instr,
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struct pt_regs *regs, union offset_union offset)
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{
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if (!LDST_U_BIT(instr))
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offset.un = -offset.un;
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if (!LDST_P_BIT(instr))
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addr += offset.un;
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if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
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regs->uregs[RN_BITS(instr)] = addr;
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}
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static int
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do_alignment_ldrhstrh(unsigned long addr, unsigned long instr,
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struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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/* old value 0x40002120, can't judge swap instr correctly */
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if ((instr & 0x4b003fe0) == 0x40000120)
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goto swp;
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if (LDST_L_BIT(instr)) {
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unsigned long val;
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get16_unaligned_check(val, addr);
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/* signed half-word? */
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if (instr & 0x80)
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val = (signed long)((signed short)val);
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regs->uregs[rd] = val;
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} else
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put16_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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swp:
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/* only handle swap word
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* for swap byte should not active this alignment exception */
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get32_unaligned_check(regs->uregs[RD_BITS(instr)], addr);
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put32_unaligned_check(regs->uregs[RM_BITS(instr)], addr);
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return TYPE_SWAP;
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fault:
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return TYPE_FAULT;
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}
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static int
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do_alignment_ldrstr(unsigned long addr, unsigned long instr,
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struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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if (!LDST_P_BIT(instr) && LDST_W_BIT(instr))
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goto trans;
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if (LDST_L_BIT(instr))
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get32_unaligned_check(regs->uregs[rd], addr);
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else
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put32_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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trans:
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if (LDST_L_BIT(instr))
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get32t_unaligned_check(regs->uregs[rd], addr);
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else
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put32t_unaligned_check(regs->uregs[rd], addr);
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return TYPE_LDST;
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fault:
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return TYPE_FAULT;
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}
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/*
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* LDM/STM alignment handler.
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*
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* There are 4 variants of this instruction:
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*
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* B = rn pointer before instruction, A = rn pointer after instruction
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* ------ increasing address ----->
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* | | r0 | r1 | ... | rx | |
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* PU = 01 B A
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* PU = 11 B A
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* PU = 00 A B
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* PU = 10 A B
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*/
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static int
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do_alignment_ldmstm(unsigned long addr, unsigned long instr,
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struct pt_regs *regs)
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{
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unsigned int rd, rn, pc_correction, reg_correction, nr_regs, regbits;
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unsigned long eaddr, newaddr;
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if (LDM_S_BIT(instr))
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goto bad;
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pc_correction = 4; /* processor implementation defined */
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/* count the number of registers in the mask to be transferred */
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nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
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rn = RN_BITS(instr);
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newaddr = eaddr = regs->uregs[rn];
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if (!LDST_U_BIT(instr))
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nr_regs = -nr_regs;
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newaddr += nr_regs;
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if (!LDST_U_BIT(instr))
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eaddr = newaddr;
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if (LDST_P_EQ_U(instr)) /* U = P */
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eaddr += 4;
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/*
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* This is a "hint" - we already have eaddr worked out by the
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* processor for us.
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*/
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if (addr != eaddr) {
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printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
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"addr = %08lx, eaddr = %08lx\n",
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instruction_pointer(regs), instr, addr, eaddr);
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show_regs(regs);
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}
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if (LDM_H_BIT(instr))
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reg_correction = 0x10;
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else
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reg_correction = 0x00;
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for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
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regbits >>= 1, rd += 1)
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if (regbits & 1) {
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if (LDST_L_BIT(instr))
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get32_unaligned_check(regs->
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uregs[rd + reg_correction], eaddr);
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else
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put32_unaligned_check(regs->
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uregs[rd + reg_correction], eaddr);
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eaddr += 4;
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}
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if (LDST_W_BIT(instr))
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regs->uregs[rn] = newaddr;
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return TYPE_DONE;
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fault:
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regs->UCreg_pc -= pc_correction;
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return TYPE_FAULT;
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bad:
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printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
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return TYPE_ERROR;
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}
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static int
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do_alignment(unsigned long addr, unsigned int error_code, struct pt_regs *regs)
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{
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union offset_union offset;
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unsigned long instr, instrptr;
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int (*handler) (unsigned long addr, unsigned long instr,
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struct pt_regs *regs);
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unsigned int type;
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instrptr = instruction_pointer(regs);
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if (instrptr >= PAGE_OFFSET)
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instr = *(unsigned long *)instrptr;
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else {
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__asm__ __volatile__(
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"ldw.u %0, [%1]\n"
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: "=&r"(instr)
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: "r"(instrptr));
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}
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regs->UCreg_pc += 4;
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switch (CODING_BITS(instr)) {
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case 0x40000120: /* ldrh or strh */
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if (LDSTH_I_BIT(instr))
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offset.un = (instr & 0x3e00) >> 4 | (instr & 31);
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else
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offset.un = regs->uregs[RM_BITS(instr)];
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handler = do_alignment_ldrhstrh;
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break;
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case 0x60000000: /* ldr or str immediate */
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case 0x60000100: /* ldr or str immediate */
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case 0x60000020: /* ldr or str immediate */
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case 0x60000120: /* ldr or str immediate */
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offset.un = OFFSET_BITS(instr);
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handler = do_alignment_ldrstr;
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break;
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case 0x40000000: /* ldr or str register */
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offset.un = regs->uregs[RM_BITS(instr)];
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{
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unsigned int shiftval = SHIFT_BITS(instr);
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switch (SHIFT_TYPE(instr)) {
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case SHIFT_LSL:
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offset.un <<= shiftval;
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break;
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case SHIFT_LSR:
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offset.un >>= shiftval;
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break;
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case SHIFT_ASR:
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offset.sn >>= shiftval;
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break;
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case SHIFT_RORRRX:
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if (shiftval == 0) {
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offset.un >>= 1;
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if (regs->UCreg_asr & PSR_C_BIT)
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offset.un |= 1 << 31;
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} else
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offset.un = offset.un >> shiftval |
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offset.un << (32 - shiftval);
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break;
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}
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}
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handler = do_alignment_ldrstr;
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break;
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case 0x80000000: /* ldm or stm */
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case 0x80000020: /* ldm or stm */
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handler = do_alignment_ldmstm;
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break;
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default:
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goto bad;
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}
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type = handler(addr, instr, regs);
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if (type == TYPE_ERROR || type == TYPE_FAULT)
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goto bad_or_fault;
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if (type == TYPE_LDST)
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do_alignment_finish_ldst(addr, instr, regs, offset);
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return 0;
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bad_or_fault:
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if (type == TYPE_ERROR)
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goto bad;
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regs->UCreg_pc -= 4;
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/*
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* We got a fault - fix it up, or die.
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*/
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do_bad_area(addr, error_code, regs);
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return 0;
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bad:
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/*
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* Oops, we didn't handle the instruction.
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* However, we must handle fpu instr firstly.
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*/
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#ifdef CONFIG_UNICORE_FPU_F64
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/* handle co.load/store */
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#define CODING_COLS 0xc0000000
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#define COLS_OFFSET_BITS(i) (i & 0x1FF)
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#define COLS_L_BITS(i) (i & (1<<24))
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#define COLS_FN_BITS(i) ((i>>14) & 31)
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if ((instr & 0xe0000000) == CODING_COLS) {
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unsigned int fn = COLS_FN_BITS(instr);
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unsigned long val = 0;
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if (COLS_L_BITS(instr)) {
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get32t_unaligned_check(val, addr);
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switch (fn) {
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#define ASM_MTF(n) case n: \
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__asm__ __volatile__("MTF %0, F" __stringify(n) \
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: : "r"(val)); \
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break;
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ASM_MTF(0); ASM_MTF(1); ASM_MTF(2); ASM_MTF(3);
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ASM_MTF(4); ASM_MTF(5); ASM_MTF(6); ASM_MTF(7);
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ASM_MTF(8); ASM_MTF(9); ASM_MTF(10); ASM_MTF(11);
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ASM_MTF(12); ASM_MTF(13); ASM_MTF(14); ASM_MTF(15);
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ASM_MTF(16); ASM_MTF(17); ASM_MTF(18); ASM_MTF(19);
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ASM_MTF(20); ASM_MTF(21); ASM_MTF(22); ASM_MTF(23);
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ASM_MTF(24); ASM_MTF(25); ASM_MTF(26); ASM_MTF(27);
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ASM_MTF(28); ASM_MTF(29); ASM_MTF(30); ASM_MTF(31);
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#undef ASM_MTF
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}
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} else {
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switch (fn) {
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#define ASM_MFF(n) case n: \
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__asm__ __volatile__("MFF %0, F" __stringify(n) \
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: : "r"(val)); \
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break;
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ASM_MFF(0); ASM_MFF(1); ASM_MFF(2); ASM_MFF(3);
|
|
ASM_MFF(4); ASM_MFF(5); ASM_MFF(6); ASM_MFF(7);
|
|
ASM_MFF(8); ASM_MFF(9); ASM_MFF(10); ASM_MFF(11);
|
|
ASM_MFF(12); ASM_MFF(13); ASM_MFF(14); ASM_MFF(15);
|
|
ASM_MFF(16); ASM_MFF(17); ASM_MFF(18); ASM_MFF(19);
|
|
ASM_MFF(20); ASM_MFF(21); ASM_MFF(22); ASM_MFF(23);
|
|
ASM_MFF(24); ASM_MFF(25); ASM_MFF(26); ASM_MFF(27);
|
|
ASM_MFF(28); ASM_MFF(29); ASM_MFF(30); ASM_MFF(31);
|
|
#undef ASM_MFF
|
|
}
|
|
put32t_unaligned_check(val, addr);
|
|
}
|
|
return TYPE_COLS;
|
|
}
|
|
fault:
|
|
return TYPE_FAULT;
|
|
#endif
|
|
printk(KERN_ERR "Alignment trap: not handling instruction "
|
|
"%08lx at [<%08lx>]\n", instr, instrptr);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* This needs to be done after sysctl_init, otherwise sys/ will be
|
|
* overwritten. Actually, this shouldn't be in sys/ at all since
|
|
* it isn't a sysctl, and it doesn't contain sysctl information.
|
|
*/
|
|
static int __init alignment_init(void)
|
|
{
|
|
hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
|
|
"alignment exception");
|
|
|
|
return 0;
|
|
}
|
|
|
|
fs_initcall(alignment_init);
|