995 lines
25 KiB
C
995 lines
25 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PROCESSOR_H
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#define _ASM_X86_PROCESSOR_H
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#include <asm/processor-flags.h>
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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struct vm86;
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/types.h>
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#include <uapi/asm/sigcontext.h>
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#include <asm/current.h>
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#include <asm/cpufeatures.h>
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#include <asm/page.h>
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#include <asm/pgtable_types.h>
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#include <asm/percpu.h>
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#include <asm/msr.h>
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#include <asm/desc_defs.h>
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#include <asm/nops.h>
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#include <asm/special_insns.h>
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#include <asm/fpu/types.h>
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#include <asm/unwind_hints.h>
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#include <asm/vdso/processor.h>
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#include <linux/personality.h>
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <linux/math64.h>
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#include <linux/err.h>
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#include <linux/irqflags.h>
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#include <linux/mem_encrypt.h>
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be quite expensive on some Nehalem processors.
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#define HBP_NUM 4
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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static inline void *current_text_addr(void)
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{
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void *pc;
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asm volatile("mov $1f, %0; 1:":"=r" (pc));
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return pc;
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}
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/*
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* These alignment constraints are for performance in the vSMP case,
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* but in the task_struct case we must also meet hardware imposed
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* alignment requirements of the FPU state:
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*/
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#ifdef CONFIG_X86_VSMP
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# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
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# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
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#else
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# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
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# define ARCH_MIN_MMSTRUCT_ALIGN 0
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#endif
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enum tlb_infos {
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ENTRIES,
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NR_INFO
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};
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extern u16 __read_mostly tlb_lli_4k[NR_INFO];
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extern u16 __read_mostly tlb_lli_2m[NR_INFO];
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extern u16 __read_mostly tlb_lli_4m[NR_INFO];
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extern u16 __read_mostly tlb_lld_4k[NR_INFO];
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extern u16 __read_mostly tlb_lld_2m[NR_INFO];
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extern u16 __read_mostly tlb_lld_4m[NR_INFO];
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extern u16 __read_mostly tlb_lld_1g[NR_INFO];
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head_32.S, so think twice
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* before touching them. [mj]
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_stepping;
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#ifdef CONFIG_X86_64
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/* Number of 4K pages in DTLB/ITLB combined(in pages): */
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int x86_tlbsize;
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#endif
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__u8 x86_virt_bits;
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__u8 x86_phys_bits;
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/* CPUID returned core id bits: */
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__u8 x86_coreid_bits;
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__u8 cu_id;
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/* Max extended CPUID function supported: */
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__u32 extended_cpuid_level;
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/* Maximum supported CPUID level, -1=no CPUID: */
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int cpuid_level;
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__u32 x86_capability[NCAPINTS + NBUGINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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/* in KB - valid for CPUS which support this call: */
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unsigned int x86_cache_size;
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int x86_cache_alignment; /* In bytes */
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/* Cache QoS architectural values: */
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int x86_cache_max_rmid; /* max index */
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int x86_cache_occ_scale; /* scale to bytes */
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int x86_power;
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unsigned long loops_per_jiffy;
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/* cpuid returned max cores value: */
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u16 x86_max_cores;
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u16 apicid;
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u16 initial_apicid;
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u16 x86_clflush_size;
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/* number of cores as seen by the OS: */
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u16 booted_cores;
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/* Physical processor id: */
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u16 phys_proc_id;
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/* Logical processor id: */
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u16 logical_proc_id;
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/* Core id: */
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u16 cpu_core_id;
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/* Index into per_cpu list: */
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u16 cpu_index;
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u32 microcode;
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/* Address space bits used by the cache internally */
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u8 x86_cache_bits;
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unsigned initialized : 1;
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} __randomize_layout;
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struct cpuid_regs {
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u32 eax, ebx, ecx, edx;
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};
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enum cpuid_regs_idx {
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CPUID_EAX = 0,
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CPUID_EBX,
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CPUID_ECX,
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CPUID_EDX,
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};
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct x86_hw_tss doublefault_tss;
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extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
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extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
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#ifdef CONFIG_SMP
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DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
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#define cpu_data(cpu) per_cpu(cpu_info, cpu)
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#else
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#define cpu_info boot_cpu_data
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#define cpu_data(cpu) boot_cpu_data
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#endif
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extern const struct seq_operations cpuinfo_op;
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#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
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extern void cpu_detect(struct cpuinfo_x86 *c);
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static inline unsigned long long l1tf_pfn_limit(void)
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{
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return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
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}
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extern void early_cpu_init(void);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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void print_cpu_msr(struct cpuinfo_x86 *);
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#ifdef CONFIG_X86_32
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extern int have_cpuid_p(void);
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#else
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static inline int have_cpuid_p(void)
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{
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return 1;
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}
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#endif
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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asm volatile("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx)
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: "memory");
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}
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#define native_cpuid_reg(reg) \
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static inline unsigned int native_cpuid_##reg(unsigned int op) \
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{ \
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unsigned int eax = op, ebx, ecx = 0, edx; \
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\
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native_cpuid(&eax, &ebx, &ecx, &edx); \
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\
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return reg; \
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}
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/*
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* Native CPUID functions returning a single datum.
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*/
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native_cpuid_reg(eax)
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native_cpuid_reg(ebx)
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native_cpuid_reg(ecx)
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native_cpuid_reg(edx)
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/*
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* Friendlier CR3 helpers.
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*/
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static inline unsigned long read_cr3_pa(void)
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{
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return __read_cr3() & CR3_ADDR_MASK;
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}
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static inline unsigned long native_read_cr3_pa(void)
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{
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return __native_read_cr3() & CR3_ADDR_MASK;
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}
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static inline void load_cr3(pgd_t *pgdir)
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{
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write_cr3(__sme_pa(pgdir));
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}
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/*
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* Note that while the legacy 'TSS' name comes from 'Task State Segment',
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* on modern x86 CPUs the TSS also holds information important to 64-bit mode,
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* unrelated to the task-switch mechanism:
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*/
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#ifdef CONFIG_X86_32
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/* This is the TSS defined by the hardware. */
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struct x86_hw_tss {
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unsigned short back_link, __blh;
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unsigned long sp0;
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unsigned short ss0, __ss0h;
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unsigned long sp1;
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/*
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* We don't use ring 1, so ss1 is a convenient scratch space in
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* the same cacheline as sp0. We use ss1 to cache the value in
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* MSR_IA32_SYSENTER_CS. When we context switch
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* MSR_IA32_SYSENTER_CS, we first check if the new value being
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* written matches ss1, and, if it's not, then we wrmsr the new
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* value and update ss1.
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*
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* The only reason we context switch MSR_IA32_SYSENTER_CS is
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* that we set it to zero in vm86 tasks to avoid corrupting the
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* stack if we were to go through the sysenter path from vm86
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* mode.
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*/
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unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
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unsigned short __ss1h;
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unsigned long sp2;
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unsigned short ss2, __ss2h;
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unsigned long __cr3;
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unsigned long ip;
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unsigned long flags;
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unsigned long ax;
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unsigned long cx;
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unsigned long dx;
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unsigned long bx;
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unsigned long sp;
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unsigned long bp;
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unsigned long si;
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unsigned long di;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace;
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unsigned short io_bitmap_base;
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} __attribute__((packed));
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#else
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struct x86_hw_tss {
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u32 reserved1;
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u64 sp0;
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/*
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* We store cpu_current_top_of_stack in sp1 so it's always accessible.
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* Linux does not use ring 1, so sp1 is not otherwise needed.
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*/
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u64 sp1;
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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} __attribute__((packed));
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#endif
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/*
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* IO-bitmap sizes:
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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struct entry_stack {
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char stack[PAGE_SIZE];
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};
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struct entry_stack_page {
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struct entry_stack stack;
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} __aligned(PAGE_SIZE);
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struct tss_struct {
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/*
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* The fixed hardware portion. This must not cross a page boundary
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* at risk of violating the SDM's advice and potentially triggering
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* errata.
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*/
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struct x86_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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} __aligned(PAGE_SIZE);
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DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
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/*
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* sizeof(unsigned long) coming from an extra "long" at the end
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* of the iobitmap.
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*
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* -1? seg base+limit should be pointing to the address of the
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* last valid byte
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*/
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#define __KERNEL_TSS_LIMIT \
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(IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
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#ifdef CONFIG_X86_32
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DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
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#else
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/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
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#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
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#endif
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/*
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* Save the original ist values for checking stack pointers during debugging
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*/
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struct orig_ist {
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unsigned long ist[7];
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};
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#ifdef CONFIG_X86_64
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DECLARE_PER_CPU(struct orig_ist, orig_ist);
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union irq_stack_union {
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char irq_stack[IRQ_STACK_SIZE];
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/*
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* GCC hardcodes the stack canary as %gs:40. Since the
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* irq_stack is the object at %gs:0, we reserve the bottom
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* 48 bytes of the irq stack for the canary.
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*/
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struct {
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char gs_base[40];
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unsigned long stack_canary;
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};
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};
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DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
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DECLARE_INIT_PER_CPU(irq_stack_union);
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static inline unsigned long cpu_kernelmode_gs_base(int cpu)
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{
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return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu);
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}
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DECLARE_PER_CPU(char *, irq_stack_ptr);
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DECLARE_PER_CPU(unsigned int, irq_count);
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extern asmlinkage void ignore_sysret(void);
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#if IS_ENABLED(CONFIG_KVM)
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/* Save actual FS/GS selectors and bases to current->thread */
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void save_fsgs_for_kvm(void);
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#endif
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#else /* X86_64 */
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#ifdef CONFIG_STACKPROTECTOR
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/*
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* Make sure stack canary segment base is cached-aligned:
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* "For Intel Atom processors, avoid non zero segment base address
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* that is not aligned to cache line boundary at all cost."
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* (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
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*/
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struct stack_canary {
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char __pad[20]; /* canary at %gs:20 */
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unsigned long canary;
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};
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DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
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#endif
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/*
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* per-CPU IRQ handling stacks
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*/
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struct irq_stack {
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u32 stack[THREAD_SIZE/sizeof(u32)];
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} __aligned(THREAD_SIZE);
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DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
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DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
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#endif /* X86_64 */
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extern unsigned int fpu_kernel_xstate_size;
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extern unsigned int fpu_user_xstate_size;
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struct perf_event;
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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struct thread_struct {
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/* Cached TLS descriptors: */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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#ifdef CONFIG_X86_32
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unsigned long sp0;
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#endif
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unsigned long sp;
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#ifdef CONFIG_X86_32
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unsigned long sysenter_cs;
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#else
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unsigned short es;
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unsigned short ds;
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unsigned short fsindex;
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unsigned short gsindex;
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#endif
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#ifdef CONFIG_X86_64
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unsigned long fsbase;
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unsigned long gsbase;
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#else
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/*
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* XXX: this could presumably be unsigned short. Alternatively,
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* 32-bit kernels could be taught to use fsindex instead.
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*/
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unsigned long fs;
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unsigned long gs;
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#endif
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/* Save middle states of ptrace breakpoints */
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struct perf_event *ptrace_bps[HBP_NUM];
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/* Debug status used for traps, single steps, etc... */
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unsigned long debugreg6;
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/* Keep track of the exact dr7 value set by the user */
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unsigned long ptrace_dr7;
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/* Fault info: */
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unsigned long cr2;
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unsigned long trap_nr;
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unsigned long error_code;
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#ifdef CONFIG_VM86
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/* Virtual 86 mode info */
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struct vm86 *vm86;
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#endif
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/* IO permissions: */
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unsigned long *io_bitmap_ptr;
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unsigned long iopl;
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/* Max allowed port in the bitmap, in bytes: */
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unsigned io_bitmap_max;
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mm_segment_t addr_limit;
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unsigned int sig_on_uaccess_err:1;
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unsigned int uaccess_err:1; /* uaccess failed */
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/* Floating point and extended processor state */
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struct fpu fpu;
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/*
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* WARNING: 'fpu' is dynamically-sized. It *MUST* be at
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* the end.
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*/
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};
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/* Whitelist the FPU state from the task_struct for hardened usercopy. */
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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unsigned long *size)
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{
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*offset = offsetof(struct thread_struct, fpu.state);
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*size = fpu_kernel_xstate_size;
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}
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/*
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* Set IOPL bits in EFLAGS from given mask
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*/
|
|
static inline void native_set_iopl_mask(unsigned mask)
|
|
{
|
|
#ifdef CONFIG_X86_32
|
|
unsigned int reg;
|
|
|
|
asm volatile ("pushfl;"
|
|
"popl %0;"
|
|
"andl %1, %0;"
|
|
"orl %2, %0;"
|
|
"pushl %0;"
|
|
"popfl"
|
|
: "=&r" (reg)
|
|
: "i" (~X86_EFLAGS_IOPL), "r" (mask));
|
|
#endif
|
|
}
|
|
|
|
static inline void
|
|
native_load_sp0(unsigned long sp0)
|
|
{
|
|
this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
|
|
}
|
|
|
|
static inline void native_swapgs(void)
|
|
{
|
|
#ifdef CONFIG_X86_64
|
|
asm volatile("swapgs" ::: "memory");
|
|
#endif
|
|
}
|
|
|
|
static inline unsigned long current_top_of_stack(void)
|
|
{
|
|
/*
|
|
* We can't read directly from tss.sp0: sp0 on x86_32 is special in
|
|
* and around vm86 mode and sp0 on x86_64 is special because of the
|
|
* entry trampoline.
|
|
*/
|
|
return this_cpu_read_stable(cpu_current_top_of_stack);
|
|
}
|
|
|
|
static inline bool on_thread_stack(void)
|
|
{
|
|
return (unsigned long)(current_top_of_stack() -
|
|
current_stack_pointer) < THREAD_SIZE;
|
|
}
|
|
|
|
#ifdef CONFIG_PARAVIRT
|
|
#include <asm/paravirt.h>
|
|
#else
|
|
#define __cpuid native_cpuid
|
|
|
|
static inline void load_sp0(unsigned long sp0)
|
|
{
|
|
native_load_sp0(sp0);
|
|
}
|
|
|
|
#define set_iopl_mask native_set_iopl_mask
|
|
#endif /* CONFIG_PARAVIRT */
|
|
|
|
/* Free all resources held by a thread. */
|
|
extern void release_thread(struct task_struct *);
|
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
/*
|
|
* Generic CPUID function
|
|
* clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
|
|
* resulting in stale register contents being returned.
|
|
*/
|
|
static inline void cpuid(unsigned int op,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = 0;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/* Some CPUID calls want 'count' to be placed in ecx */
|
|
static inline void cpuid_count(unsigned int op, int count,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = count;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/*
|
|
* CPUID functions returning a single datum
|
|
*/
|
|
static inline unsigned int cpuid_eax(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return eax;
|
|
}
|
|
|
|
static inline unsigned int cpuid_ebx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return ebx;
|
|
}
|
|
|
|
static inline unsigned int cpuid_ecx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return ecx;
|
|
}
|
|
|
|
static inline unsigned int cpuid_edx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
|
|
return edx;
|
|
}
|
|
|
|
/*
|
|
* This function forces the icache and prefetched instruction stream to
|
|
* catch up with reality in two very specific cases:
|
|
*
|
|
* a) Text was modified using one virtual address and is about to be executed
|
|
* from the same physical page at a different virtual address.
|
|
*
|
|
* b) Text was modified on a different CPU, may subsequently be
|
|
* executed on this CPU, and you want to make sure the new version
|
|
* gets executed. This generally means you're calling this in a IPI.
|
|
*
|
|
* If you're calling this for a different reason, you're probably doing
|
|
* it wrong.
|
|
*/
|
|
static inline void sync_core(void)
|
|
{
|
|
/*
|
|
* There are quite a few ways to do this. IRET-to-self is nice
|
|
* because it works on every CPU, at any CPL (so it's compatible
|
|
* with paravirtualization), and it never exits to a hypervisor.
|
|
* The only down sides are that it's a bit slow (it seems to be
|
|
* a bit more than 2x slower than the fastest options) and that
|
|
* it unmasks NMIs. The "push %cs" is needed because, in
|
|
* paravirtual environments, __KERNEL_CS may not be a valid CS
|
|
* value when we do IRET directly.
|
|
*
|
|
* In case NMI unmasking or performance ever becomes a problem,
|
|
* the next best option appears to be MOV-to-CR2 and an
|
|
* unconditional jump. That sequence also works on all CPUs,
|
|
* but it will fault at CPL3 (i.e. Xen PV).
|
|
*
|
|
* CPUID is the conventional way, but it's nasty: it doesn't
|
|
* exist on some 486-like CPUs, and it usually exits to a
|
|
* hypervisor.
|
|
*
|
|
* Like all of Linux's memory ordering operations, this is a
|
|
* compiler barrier as well.
|
|
*/
|
|
#ifdef CONFIG_X86_32
|
|
asm volatile (
|
|
"pushfl\n\t"
|
|
"pushl %%cs\n\t"
|
|
"pushl $1f\n\t"
|
|
"iret\n\t"
|
|
"1:"
|
|
: ASM_CALL_CONSTRAINT : : "memory");
|
|
#else
|
|
unsigned int tmp;
|
|
|
|
asm volatile (
|
|
UNWIND_HINT_SAVE
|
|
"mov %%ss, %0\n\t"
|
|
"pushq %q0\n\t"
|
|
"pushq %%rsp\n\t"
|
|
"addq $8, (%%rsp)\n\t"
|
|
"pushfq\n\t"
|
|
"mov %%cs, %0\n\t"
|
|
"pushq %q0\n\t"
|
|
"pushq $1f\n\t"
|
|
"iretq\n\t"
|
|
UNWIND_HINT_RESTORE
|
|
"1:"
|
|
: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
|
|
#endif
|
|
}
|
|
|
|
extern void select_idle_routine(const struct cpuinfo_x86 *c);
|
|
extern void amd_e400_c1e_apic_setup(void);
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
|
|
enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
|
|
IDLE_POLL};
|
|
|
|
extern void enable_sep_cpu(void);
|
|
extern int sysenter_setup(void);
|
|
|
|
void early_trap_pf_init(void);
|
|
|
|
/* Defined in head.S */
|
|
extern struct desc_ptr early_gdt_descr;
|
|
|
|
extern void switch_to_new_gdt(int);
|
|
extern void load_direct_gdt(int);
|
|
extern void load_fixmap_gdt(int);
|
|
extern void load_percpu_segment(int);
|
|
extern void cpu_init(void);
|
|
|
|
static inline unsigned long get_debugctlmsr(void)
|
|
{
|
|
unsigned long debugctlmsr = 0;
|
|
|
|
#ifndef CONFIG_X86_DEBUGCTLMSR
|
|
if (boot_cpu_data.x86 < 6)
|
|
return 0;
|
|
#endif
|
|
rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
|
|
|
|
return debugctlmsr;
|
|
}
|
|
|
|
static inline void update_debugctlmsr(unsigned long debugctlmsr)
|
|
{
|
|
#ifndef CONFIG_X86_DEBUGCTLMSR
|
|
if (boot_cpu_data.x86 < 6)
|
|
return;
|
|
#endif
|
|
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
|
|
}
|
|
|
|
extern void set_task_blockstep(struct task_struct *task, bool on);
|
|
|
|
/* Boot loader type from the setup header: */
|
|
extern int bootloader_type;
|
|
extern int bootloader_version;
|
|
|
|
extern char ignore_fpu_irq;
|
|
|
|
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
#ifdef CONFIG_X86_32
|
|
# define BASE_PREFETCH ""
|
|
# define ARCH_HAS_PREFETCH
|
|
#else
|
|
# define BASE_PREFETCH "prefetcht0 %P1"
|
|
#endif
|
|
|
|
/*
|
|
* Prefetch instructions for Pentium III (+) and AMD Athlon (+)
|
|
*
|
|
* It's not worth to care about 3dnow prefetches for the K6
|
|
* because they are microcoded there and very slow.
|
|
*/
|
|
static inline void prefetch(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH, "prefetchnta %P1",
|
|
X86_FEATURE_XMM,
|
|
"m" (*(const char *)x));
|
|
}
|
|
|
|
/*
|
|
* 3dnow prefetch to get an exclusive cache line.
|
|
* Useful for spinlocks to avoid one state transition in the
|
|
* cache coherency protocol:
|
|
*/
|
|
static inline void prefetchw(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH, "prefetchw %P1",
|
|
X86_FEATURE_3DNOWPREFETCH,
|
|
"m" (*(const char *)x));
|
|
}
|
|
|
|
static inline void spin_lock_prefetch(const void *x)
|
|
{
|
|
prefetchw(x);
|
|
}
|
|
|
|
#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
|
|
TOP_OF_KERNEL_STACK_PADDING)
|
|
|
|
#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
|
|
|
|
#define task_pt_regs(task) \
|
|
({ \
|
|
unsigned long __ptr = (unsigned long)task_stack_page(task); \
|
|
__ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
|
|
((struct pt_regs *)__ptr) - 1; \
|
|
})
|
|
|
|
#ifdef CONFIG_X86_32
|
|
/*
|
|
* User space process size: 3GB (default).
|
|
*/
|
|
#define IA32_PAGE_OFFSET PAGE_OFFSET
|
|
#define TASK_SIZE PAGE_OFFSET
|
|
#define TASK_SIZE_LOW TASK_SIZE
|
|
#define TASK_SIZE_MAX TASK_SIZE
|
|
#define DEFAULT_MAP_WINDOW TASK_SIZE
|
|
#define STACK_TOP TASK_SIZE
|
|
#define STACK_TOP_MAX STACK_TOP
|
|
|
|
#define INIT_THREAD { \
|
|
.sp0 = TOP_OF_INIT_STACK, \
|
|
.sysenter_cs = __KERNEL_CS, \
|
|
.io_bitmap_ptr = NULL, \
|
|
.addr_limit = KERNEL_DS, \
|
|
}
|
|
|
|
#define KSTK_ESP(task) (task_pt_regs(task)->sp)
|
|
|
|
#else
|
|
/*
|
|
* User space process size. This is the first address outside the user range.
|
|
* There are a few constraints that determine this:
|
|
*
|
|
* On Intel CPUs, if a SYSCALL instruction is at the highest canonical
|
|
* address, then that syscall will enter the kernel with a
|
|
* non-canonical return address, and SYSRET will explode dangerously.
|
|
* We avoid this particular problem by preventing anything executable
|
|
* from being mapped at the maximum canonical address.
|
|
*
|
|
* On AMD CPUs in the Ryzen family, there's a nasty bug in which the
|
|
* CPUs malfunction if they execute code from the highest canonical page.
|
|
* They'll speculate right off the end of the canonical space, and
|
|
* bad things happen. This is worked around in the same way as the
|
|
* Intel problem.
|
|
*
|
|
* With page table isolation enabled, we map the LDT in ... [stay tuned]
|
|
*/
|
|
#define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
|
|
|
|
#define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
|
|
|
|
/* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
|
|
0xc0000000 : 0xFFFFe000)
|
|
|
|
#define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
|
|
IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
|
|
#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE_MAX)
|
|
#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE_MAX)
|
|
|
|
#define STACK_TOP TASK_SIZE_LOW
|
|
#define STACK_TOP_MAX TASK_SIZE_MAX
|
|
|
|
#define INIT_THREAD { \
|
|
.addr_limit = KERNEL_DS, \
|
|
}
|
|
|
|
extern unsigned long KSTK_ESP(struct task_struct *task);
|
|
|
|
#endif /* CONFIG_X86_64 */
|
|
|
|
extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
|
|
unsigned long new_sp);
|
|
|
|
/*
|
|
* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
|
|
#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
|
|
|
|
#define KSTK_EIP(task) (task_pt_regs(task)->ip)
|
|
|
|
/* Get/set a process' ability to use the timestamp counter instruction */
|
|
#define GET_TSC_CTL(adr) get_tsc_mode((adr))
|
|
#define SET_TSC_CTL(val) set_tsc_mode((val))
|
|
|
|
extern int get_tsc_mode(unsigned long adr);
|
|
extern int set_tsc_mode(unsigned int val);
|
|
|
|
DECLARE_PER_CPU(u64, msr_misc_features_shadow);
|
|
|
|
/* Register/unregister a process' MPX related resource */
|
|
#define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
|
|
#define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
|
|
|
|
#ifdef CONFIG_X86_INTEL_MPX
|
|
extern int mpx_enable_management(void);
|
|
extern int mpx_disable_management(void);
|
|
#else
|
|
static inline int mpx_enable_management(void)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
static inline int mpx_disable_management(void)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif /* CONFIG_X86_INTEL_MPX */
|
|
|
|
#ifdef CONFIG_CPU_SUP_AMD
|
|
extern u16 amd_get_nb_id(int cpu);
|
|
extern u32 amd_get_nodes_per_socket(void);
|
|
#else
|
|
static inline u16 amd_get_nb_id(int cpu) { return 0; }
|
|
static inline u32 amd_get_nodes_per_socket(void) { return 0; }
|
|
#endif
|
|
|
|
static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
|
|
{
|
|
uint32_t base, eax, signature[3];
|
|
|
|
for (base = 0x40000000; base < 0x40010000; base += 0x100) {
|
|
cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
|
|
|
|
if (!memcmp(sig, signature, 12) &&
|
|
(leaves == 0 || ((eax - base) >= leaves)))
|
|
return base;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
extern unsigned long arch_align_stack(unsigned long sp);
|
|
extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
|
|
extern void free_kernel_image_pages(void *begin, void *end);
|
|
|
|
void default_idle(void);
|
|
#ifdef CONFIG_XEN
|
|
bool xen_set_default_idle(void);
|
|
#else
|
|
#define xen_set_default_idle 0
|
|
#endif
|
|
|
|
void stop_this_cpu(void *dummy);
|
|
void df_debug(struct pt_regs *regs, long error_code);
|
|
void microcode_check(void);
|
|
|
|
enum l1tf_mitigations {
|
|
L1TF_MITIGATION_OFF,
|
|
L1TF_MITIGATION_FLUSH_NOWARN,
|
|
L1TF_MITIGATION_FLUSH,
|
|
L1TF_MITIGATION_FLUSH_NOSMT,
|
|
L1TF_MITIGATION_FULL,
|
|
L1TF_MITIGATION_FULL_FORCE
|
|
};
|
|
|
|
extern enum l1tf_mitigations l1tf_mitigation;
|
|
|
|
enum mds_mitigations {
|
|
MDS_MITIGATION_OFF,
|
|
MDS_MITIGATION_FULL,
|
|
MDS_MITIGATION_VMWERV,
|
|
};
|
|
|
|
enum taa_mitigations {
|
|
TAA_MITIGATION_OFF,
|
|
TAA_MITIGATION_UCODE_NEEDED,
|
|
TAA_MITIGATION_VERW,
|
|
TAA_MITIGATION_TSX_DISABLED,
|
|
};
|
|
|
|
#endif /* _ASM_X86_PROCESSOR_H */
|