161 lines
3.9 KiB
C
161 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6833-clk.h>
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#define MT_CLKMGR_MODULE_INIT 0
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#define MT_CCF_BRINGUP 1
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#define INV_OFS -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
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0x170, INV_OFS, BIT(20), BIT(20));
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static const struct mtk_gate_regs mdp0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mdp1_cg_regs = {
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.set_ofs = 0x124,
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.clr_ofs = 0x128,
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.sta_ofs = 0x120,
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};
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#define GATE_MDP0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MDP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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static const struct mtk_gate mdp_clks[] = {
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/* MDP0 */
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GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0",
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"mdp_ck"/* parent */, 0),
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GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0",
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"mdp_ck"/* parent */, 1),
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GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0",
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"mdp_ck"/* parent */, 2),
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GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1",
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"mdp_ck"/* parent */, 3),
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GATE_MDP0(CLK_MDP_RDMA1, "mdp_rdma1",
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"mdp_ck"/* parent */, 4),
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GATE_MDP0(CLK_MDP_TDSHP1, "mdp_tdshp1",
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"mdp_ck"/* parent */, 5),
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GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0",
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"mdp_ck"/* parent */, 6),
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GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus",
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"mdp_ck"/* parent */, 7),
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GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0",
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"mdp_ck"/* parent */, 8),
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GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0",
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"mdp_ck"/* parent */, 9),
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GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0",
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"mdp_ck"/* parent */, 10),
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GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0",
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"mdp_ck"/* parent */, 11),
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GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1",
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"mdp_ck"/* parent */, 12),
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GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1",
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"mdp_ck"/* parent */, 13),
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GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0",
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"mdp_ck"/* parent */, 14),
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GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0",
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"mdp_ck"/* parent */, 15),
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GATE_MDP0(CLK_MDP_AAL1, "mdp_aal1",
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"mdp_ck"/* parent */, 16),
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GATE_MDP0(CLK_MDP_COLOR0, "mdp_color0",
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"mdp_ck"/* parent */, 17),
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/* MDP1 */
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GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0",
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"mdp_ck"/* parent */, 0),
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GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1",
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"mdp_ck"/* parent */, 8),
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};
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static int clk_mt6833_mdp_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_MDP_NR_CLK);
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mtk_clk_register_gates(node, mdp_clks, ARRAY_SIZE(mdp_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_notice("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6833_mdp[] = {
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{ .compatible = "mediatek,mt6833-mdpsys_config", },
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{}
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};
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#if MT_CLKMGR_MODULE_INIT
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static struct platform_driver clk_mt6833_mdp_drv = {
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.probe = clk_mt6833_mdp_probe,
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.driver = {
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.name = "clk-mt6833-mdp",
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.of_match_table = of_match_clk_mt6833_mdp,
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},
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};
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builtin_platform_driver(clk_mt6833_mdp_drv);
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#else
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static struct platform_driver clk_mt6833_mdp_drv = {
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.probe = clk_mt6833_mdp_probe,
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.driver = {
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.name = "clk-mt6833-mdp",
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.of_match_table = of_match_clk_mt6833_mdp,
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},
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};
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static int __init clk_mt6833_mdp_platform_init(void)
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{
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return platform_driver_register(&clk_mt6833_mdp_drv);
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}
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arch_initcall(clk_mt6833_mdp_platform_init);
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#endif /* MT_CLKMGR_MODULE_INIT */
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