61 lines
1 KiB
C
61 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRV_CLKCHK_MT6877_H
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#define __DRV_CLKCHK_MT6877_H
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enum chk_sys_id {
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top = 0,
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ifrao = 1,
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infracfg_ao_bus = 2,
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spm = 3,
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apmixed = 4,
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scp_par = 5,
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audsys = 6,
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msdc0 = 7,
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impc = 8,
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impe = 9,
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imps = 10,
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impws = 11,
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impw = 12,
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impn = 13,
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mfg_ao = 14,
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mfgcfg = 15,
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mm = 16,
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imgsys1 = 17,
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imgsys2 = 18,
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vde2 = 19,
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ven1 = 20,
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apu_conn2 = 21,
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apu_conn1 = 22,
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apuv = 23,
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apu0 = 24,
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apu1 = 25,
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apum0 = 26,
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apu_ao = 27,
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cam_m = 28,
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cam_ra = 29,
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cam_rb = 30,
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ipe = 31,
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mdp = 32,
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chk_sys_num = 33,
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};
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extern const char * const *get_mt6877_all_clk_names(void);
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extern struct regbase *get_mt6877_all_reg_bases(void);
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extern struct regname *get_mt6877_all_reg_names(void);
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/*ram console api*/
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#ifdef CONFIG_MTK_RAM_CONSOLE
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extern void aee_rr_rec_clk(int id, u32 val);
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#endif
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extern void print_enabled_clks_once(void);
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extern void print_subsys_reg(enum chk_sys_id id);
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extern int get_sw_req_vcore_opp(void);
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#endif /* __DRV_CLKCHK_MT6877_H */
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