350 lines
9.5 KiB
C
350 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __MMDVFS_CONFIG_MT6765_H__
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#define __MMDVFS_CONFIG_MT6765_H__
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#include "mmdvfs_config_util.h"
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#ifdef VCORE_READY
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#include <mtk_vcorefs_manager.h>
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#else
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#define OPP_0 0
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#define OPP_1 1
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#define OPP_2 2
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#define OPP_3 3
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#endif
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/* Part I MMSVFS HW Configuration (OPP)*/
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/* Define the number of mmdvfs, vcore and mm clks opps */
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/* Max total MMDVFS opps of the profile support */
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#define MT6765_MMDVFS_OPP_MAX 5
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/* Max total CLK opps of the profile support */
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#define MT6765_MMDVFS_CLK_OPP_MAX 3
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/* Max total Vcore opps of the profile support */
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#define MT6765_MMDVFS_VCORE_OPP_MAX 4
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/* CLK source configuration */
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/* CLK source IDs */
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/* Define the internal index of each CLK source*/
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#define MT6765_CLK_TOP_MMPLL_CK 0
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#define MT6765_CLK_TOP_UNIVPLL1_D2_CK 1
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#define MT6765_CLK_TOP_MMPLL_D2_CK 2
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#define MT6765_CLK_SOURCE_NUM 3
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/* CLK Source definiation */
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/* Define the clk source description */
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struct mmdvfs_clk_source_desc mt6765_clk_sources[MT6765_CLK_SOURCE_NUM] = {
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{NULL, "mmdvfs_clk_mmpll_ck", 457},
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{NULL, "mmdvfs_clk_univpll1_d2_ck", 312},
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{NULL, "mmdvfs_clk_mmpll_d2_ck", 228},
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};
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/*
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* B. CLK Change adaption configurtion
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* B.1 Define the clk change method and data of each MM CLK step
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* Field decscription:
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* 1. config_method:
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* a. MMDVFS_CLK_CONFIG_BY_MUX
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* b. MMDVFS_CLK_CONFIG_PLL
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* c. MMDVFS_CLK_CONFIG_NONE
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* 2. pll_id: PLL ID, please set -1 if PLL hopping is not used
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* 3. clk mux desc {handle, name}, plz set -1
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* and it will be initialized by driver automaticlly
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* 4. total step: the number of the steps supported by this sub sys
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* 5. hopping dss of each steps: please set -1 if it is not used
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* 6. clk sources id of each steps: please set -1 if it is not used
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*/
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struct mmdvfs_clk_hw_map mt6765_clk_hw_map_setting[MMDVFS_CLK_MUX_NUM] = {
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_SMI0_2X_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_BY_MUX,
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{NULL, "MMDVFS_CLK_MUX_TOP_MM_SEL"}, -1, 3,
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{-1, -1},
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{MT6765_CLK_TOP_MMPLL_CK,
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MT6765_CLK_TOP_UNIVPLL1_D2_CK,
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MT6765_CLK_TOP_MMPLL_D2_CK}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_CAM_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_IMG_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_VENC_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_VDEC_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_MJC_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_VPU_IF_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_VPU_IF_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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},
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{MMDVFS_CLK_NONE,
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{NULL, "MMDVFS_CLK_MUX_TOP_VPU_SEL"}, -1, 3,
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{-1, -1, -1},
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{-1, -1, -1}
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}
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};
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struct mmdvfs_profile_mask qos_apply_profiles[] = {
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/* #ifdef MMDVFS_QOS_SUPPORT */
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/* ISP for opp0 */
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{"ISP",
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MMDVFS_PMQOS_ISP,
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MMDVFS_FINE_STEP_OPP0},
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/* ISP for opp1 */
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{"ISP",
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MMDVFS_PMQOS_ISP,
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MMDVFS_FINE_STEP_OPP2},
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/* ISP for opp2 */
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{"ISP",
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MMDVFS_PMQOS_ISP,
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MMDVFS_FINE_STEP_OPP4},
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/* ICFP for opp0 */
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{"ICFP",
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SMI_BWC_SCEN_ICFP,
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MMDVFS_FINE_STEP_OPP0},
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/* ICFP for opp1 */
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{"ICFP",
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SMI_BWC_SCEN_ICFP,
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MMDVFS_FINE_STEP_OPP1},
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/* debug entry */
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{"DEBUG",
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0,
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MMDVFS_FINE_STEP_UNREQUEST },
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};
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/* Part II MMDVFS Scenario's Step Confuguration */
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#define MT6765_MMDVFS_SENSOR_MIN (16000000)
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/* A.1 [LP4 2-ch] Scenarios of each MM DVFS Step (force kicker) */
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/* OPP 0 scenarios */
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#define MT6765_MMDVFS_OPP0_NUM 1
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struct mmdvfs_profile mt6765_mmdvfs_opp0_profiles[MT6765_MMDVFS_OPP0_NUM] = {
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{"ICFP", SMI_BWC_SCEN_ICFP, {0, 0, 0}, {0, 0, 0 } },
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};
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/* OPP 1 scenarios */
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#define MT6765_MMDVFS_OPP1_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp1_profiles[MT6765_MMDVFS_OPP1_NUM] = {
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};
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/* OPP 2 scenarios */
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#define MT6765_MMDVFS_OPP2_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp2_profiles[MT6765_MMDVFS_OPP2_NUM] = {
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};
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/* OPP 3 scenarios */
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#define MT6765_MMDVFS_OPP3_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp3_profiles[MT6765_MMDVFS_OPP3_NUM] = {
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};
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/* OPP 4 scenarios */
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#define MT6765_MMDVFS_OPP4_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp4_profiles[MT6765_MMDVFS_OPP4_NUM] = {
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};
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/* A.2 [LP3] Scenarios of each MM DVFS Step (force kicker) */
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/* OPP 0 scenarios */
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#define MT6765_LP3_MMDVFS_OPP0_NUM 1
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struct mmdvfs_profile mt6765_mmdvfs_opp0_profiles_lp3[
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MT6765_LP3_MMDVFS_OPP0_NUM] = {
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{"ICFP", SMI_BWC_SCEN_ICFP, {0, 0, 0}, {0, 0, 0 } },
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};
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/* OPP 1 scenarios */
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#define MT6765_LP3_MMDVFS_OPP1_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp1_profiles_lp3[
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MT6765_LP3_MMDVFS_OPP1_NUM] = {
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};
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/* OPP 2 scenarios */
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#define MT6765_LP3_MMDVFS_OPP2_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp2_profiles_lp3[
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MT6765_LP3_MMDVFS_OPP2_NUM] = {
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};
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/* OPP 3 scenarios */
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#define MT6765_LP3_MMDVFS_OPP3_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp3_profiles_lp3[
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MT6765_LP3_MMDVFS_OPP3_NUM] = {
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};
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/* OPP 4 scenarios */
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#define MT6765_LP3_MMDVFS_OPP4_NUM 0
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struct mmdvfs_profile mt6765_mmdvfs_opp4_profiles_lp3[
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MT6765_LP3_MMDVFS_OPP4_NUM] = {
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};
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/* Defined the smi scenarios whose DVFS is controlled by low-level driver */
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/* directly, not by BWC scenario change event */
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#define MT6765_MMDVFS_USER_CONTROL_SCEN_MASK (1 << SMI_BWC_SCEN_VP)
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struct mmdvfs_step_to_qos_step legacy_to_qos_step[MT6765_MMDVFS_OPP_MAX] = {
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{0, 0},
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{1, 0},
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{2, 1},
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{3, 1},
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{4, 2},
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};
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/* Part III Scenario and MMSVFS HW configuration mapping */
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/* 1. For a single mmdvfs step's profiles and hardware configuration */
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/* LP4 2-ch */
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struct mmdvfs_step_profile mt6765_step_profile[MT6765_MMDVFS_OPP_MAX] = {
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{0, mt6765_mmdvfs_opp0_profiles, MT6765_MMDVFS_OPP0_NUM,
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{OPP_0,
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{MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0}, MMDVFS_CLK_MUX_NUM
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}
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},
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{1, mt6765_mmdvfs_opp1_profiles, MT6765_MMDVFS_OPP1_NUM,
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{OPP_0,
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{MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0}, MMDVFS_CLK_MUX_NUM
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}
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},
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{2, mt6765_mmdvfs_opp2_profiles, MT6765_MMDVFS_OPP2_NUM,
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{OPP_1,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{3, mt6765_mmdvfs_opp3_profiles, MT6765_MMDVFS_OPP3_NUM,
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{OPP_1,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{4, mt6765_mmdvfs_opp4_profiles, MT6765_MMDVFS_OPP4_NUM,
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{OPP_3,
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{MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2}, MMDVFS_CLK_MUX_NUM
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}
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},
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};
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/* LP3 */
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struct mmdvfs_step_profile mt6765_step_profile_lp3[MT6765_MMDVFS_OPP_MAX] = {
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{0, mt6765_mmdvfs_opp0_profiles_lp3, MT6765_LP3_MMDVFS_OPP0_NUM,
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{OPP_0,
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{MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0}, MMDVFS_CLK_MUX_NUM
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}
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},
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{1, mt6765_mmdvfs_opp1_profiles_lp3, MT6765_LP3_MMDVFS_OPP1_NUM,
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{OPP_0,
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{MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0}, MMDVFS_CLK_MUX_NUM
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}
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},
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{2, mt6765_mmdvfs_opp2_profiles_lp3, MT6765_LP3_MMDVFS_OPP2_NUM,
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{OPP_1,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{3, mt6765_mmdvfs_opp3_profiles_lp3, MT6765_LP3_MMDVFS_OPP3_NUM,
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{OPP_1,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{4, mt6765_mmdvfs_opp4_profiles_lp3, MT6765_LP3_MMDVFS_OPP4_NUM,
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{OPP_3,
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{MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2,
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MMDVFS_MMCLK_OPP2, MMDVFS_MMCLK_OPP2}, MMDVFS_CLK_MUX_NUM
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}
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},
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};
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/* Part III Scenario and MMSVFS HW configuration mapping */
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/* Part IV VPU association */
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/* There is no VPU DVFS in MT6765 */
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/* Part V ISP DVFS configuration */
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#define MMDVFS_ISP_THRESHOLD_NUM 3
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int mt6765_isp_threshold_setting[MMDVFS_ISP_THRESHOLD_NUM] = {457, 312, 228};
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int mt6765_isp_threshold_opp[MMDVFS_ISP_THRESHOLD_NUM] = {
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MMDVFS_FINE_STEP_OPP0, MMDVFS_FINE_STEP_OPP2, MMDVFS_FINE_STEP_OPP4};
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struct mmdvfs_thres_setting mt6765_thres_handler[MMDVFS_PM_QOS_SUB_SYS_NUM] = {
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{ MMDVFS_PM_QOS_SUB_SYS_CAMERA, mt6765_isp_threshold_setting,
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mt6765_isp_threshold_opp,
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MMDVFS_ISP_THRESHOLD_NUM, MMDVFS_PMQOS_ISP},
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};
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#endif /* __MMDVFS_CONFIG_MT6765_H__ */
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