147 lines
4.9 KiB
C
147 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 MediaTek Inc.
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*/
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#ifndef __MUSB_DMA_H__
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#define __MUSB_DMA_H__
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struct musb_hw_ep;
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/*
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* DMA Controller Abstraction
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*
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* DMA Controllers are abstracted to allow use of a variety of different
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* implementations of DMA, as allowed by the Inventra USB cores. On the
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* host side, usbcore sets up the DMA mappings and flushes caches; on the
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* peripheral side, the gadget controller driver does. Responsibilities
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* of a DMA controller driver include:
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*
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* - Handling the details of moving multiple USB packets
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* in cooperation with the Inventra USB core, including especially
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* the correct RX side treatment of short packets and buffer-full
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* states (both of which terminate transfers).
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*
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* - Knowing the correlation between dma channels and the
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* Inventra core's local endpoint resources and data direction.
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*
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* - Maintaining a list of allocated/available channels.
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*
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* - Updating channel status on interrupts,
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* whether shared with the Inventra core or separate.
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*/
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#ifndef CONFIG_MUSB_PIO_ONLY
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#define is_dma_capable() (1)
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#else
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#define is_dma_capable() (0)
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#endif
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/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
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* Only allow DMA mode 1 to be used when the USB will actually generate the
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* interrupts we expect.
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*/
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/*
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* DMA channel status ... updated by the dma controller driver whenever that
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* status changes, and protected by the overall controller spinlock.
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*/
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enum dma_channel_status {
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/* unallocated */
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MUSB_DMA_STATUS_UNKNOWN,
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/* allocated ... but not busy, no errors */
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MUSB_DMA_STATUS_FREE,
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/* busy ... transactions are active */
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MUSB_DMA_STATUS_BUSY,
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/* transaction(s) aborted due to ... dma or memory bus error */
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MUSB_DMA_STATUS_BUS_ABORT,
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/* transaction(s) aborted due to ... core error or USB fault */
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MUSB_DMA_STATUS_CORE_ABORT
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};
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struct dma_controller;
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/**
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* struct dma_channel - A DMA channel.
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* @private_data: channel-private data
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* @max_len: the maximum number of bytes the channel can move in one
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* transaction (typically representing many USB maximum-sized packets)
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* @actual_len: how many bytes have been transferred
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* @prog_len: how many bytes have been programmed for transfer
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* @status: current channel status (updated e.g. on interrupt)
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* @desired_mode: true if mode 1 is desired; false if mode 0 is desired
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*
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* channels are associated with an endpoint for the duration of at least
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* one usb transfer.
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*/
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struct dma_channel {
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void *private_data;
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/* FIXME not void* private_data, but a dma_controller * */
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size_t max_len;
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size_t actual_len;
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size_t prog_len;
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enum dma_channel_status status;
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bool desired_mode;
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};
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/*
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* dma_channel_status - return status of dma channel
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* @c: the channel
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*
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* Returns the software's view of the channel status. If that status is BUSY
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* then it's possible that the hardware has completed (or aborted) a transfer,
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* so the driver needs to update that status.
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*/
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static inline enum dma_channel_status dma_channel_status(struct dma_channel *c)
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{
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return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
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}
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/**
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* struct dma_controller - A DMA Controller.
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* @start: call this to start a DMA controller;
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* return 0 on success, else negative errno
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* @stop: call this to stop a DMA controller
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* return 0 on success, else negative errno
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* @channel_alloc: call this to allocate a DMA channel
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* @channel_release: call this to release a DMA channel
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* @channel_abort: call this to abort a pending DMA transaction,
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* returning it to FREE (but allocated) state
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* @channel_pause: This function pauses the ongoing DMA transfer
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* @channel_resume: This function resumes the ongoing DMA transfer
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* @tx_status: Gets the residue of an ongoing DMA transfer
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* @check_resiudue: checks if the residue of an ongoing DMA
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* transfer is valid
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* Controllers manage dma channels.
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*/
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struct dma_controller {
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int (*start)(struct dma_controller *c);
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int (*stop)(struct dma_controller *c);
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struct dma_channel *(*channel_alloc)(struct dma_controller *c,
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struct musb_hw_ep *hw_ep,
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u8 is_tx);
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void (*channel_release)(struct dma_channel *channel);
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int (*channel_program)(struct dma_channel *channel,
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u16 maxpacket, u8 mode,
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dma_addr_t dma_addr, u32 length);
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int (*channel_abort)(struct dma_channel *channel);
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int (*channel_pause)(struct dma_channel *channel);
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int (*channel_resume)(struct dma_channel *channel);
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int (*tx_status)(struct dma_channel *channel);
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int (*check_residue)(struct dma_channel *channel, u32 residue);
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int (*is_compatible)(struct dma_channel *channel,
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u16 maxpacket, void *buf, u32 length);
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};
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/* called after channel_program(), may indicate a fault */
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extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
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extern struct dma_controller
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*dma_controller_create(struct musb *musb, void __iomem *base);
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extern void dma_controller_destroy(struct dma_controller *c);
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#endif /* __MUSB_DMA_H__ */
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