754 lines
20 KiB
C
754 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include <linux/stat.h>
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#include <linux/usb/composite.h>
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#include "musb_core.h"
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#include "musb_host.h"
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#include "musbhsdma.h"
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#include "mtk_musb.h"
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#include "musb_qmu.h"
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static unsigned int host_qmu_tx_max_active_isoc_gpd[MAX_QMU_EP + 1];
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static unsigned int host_qmu_tx_max_number_of_pkts[MAX_QMU_EP + 1];
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static unsigned int host_qmu_rx_max_active_isoc_gpd[MAX_QMU_EP + 1];
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static unsigned int host_qmu_rx_max_number_of_pkts[MAX_QMU_EP + 1];
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#define MTK_HOST_ACTIVE_DEV_TABLE_SZ 128
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static u8 mtk_host_active_dev_table[MTK_HOST_ACTIVE_DEV_TABLE_SZ];
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#ifdef CONFIG_MTK_UAC_POWER_SAVING
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static struct workqueue_struct *low_power_timer_test_wq;
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static struct work_struct low_power_timer_test_work;
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static int low_power_timer_activate;
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static unsigned long low_power_timer_total_sleep;
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static unsigned long low_power_timer_total_wake;
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static int low_power_timer_request_time;
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static unsigned int low_power_timer_trigger_cnt;
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static unsigned int low_power_timer_wake_cnt;
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static ktime_t ktime_wake, ktime_sleep, ktime_begin, ktime_end;
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static int low_power_timer_irq_ctrl;
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#define LOW_POWER_TIMER_MIN_PERIOD 10 /* ms */
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#define LOW_POWER_TIMER_MAX_PERIOD 50 /* ms */
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static struct delayed_work low_power_timer_montior_work;
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enum {
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IDLE_STAGE,
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RUNNING_STAGE
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};
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#define MONITOR_FREQ 6000 /* ms */
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static void do_low_power_timer_monitor_work(struct work_struct *work)
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{
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static int state = IDLE_STAGE;
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static unsigned int last_trigger_cnt;
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DBG(1, "state:%s, last:%d, balanced<%d,%d>\n",
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state?"RUNNING_STAGE":"IDLE_STAGE",
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last_trigger_cnt,
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low_power_timer_total_trigger_cnt,
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low_power_timer_total_wake_cnt);
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if (state == IDLE_STAGE) {
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if (last_trigger_cnt != low_power_timer_total_trigger_cnt)
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state = RUNNING_STAGE;
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} else if (state == RUNNING_STAGE) {
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if (last_trigger_cnt == low_power_timer_total_trigger_cnt
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&& low_power_timer_total_trigger_cnt ==
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low_power_timer_total_wake_cnt)
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state = IDLE_STAGE;
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else if (last_trigger_cnt ==
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low_power_timer_total_trigger_cnt
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&& low_power_timer_total_trigger_cnt !=
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low_power_timer_total_wake_cnt)
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musb_bug();
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}
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last_trigger_cnt = low_power_timer_total_trigger_cnt;
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schedule_delayed_work(&low_power_timer_montior_work,
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msecs_to_jiffies(MONITOR_FREQ));
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}
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static void low_power_timer_wakeup_func(unsigned long data);
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static DEFINE_TIMER(low_power_timer, low_power_timer_wakeup_func, 0, 0);
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static void low_power_timer_resource_reset(void)
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{
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low_power_timer_total_sleep = low_power_timer_total_wake = 0;
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low_power_timer_trigger_cnt = low_power_timer_wake_cnt = 0;
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}
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static void low_power_timer_wakeup_func(struct timer_list *timer)
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{
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#ifdef TIMER_LOCK
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unsigned long flags;
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spin_lock_irqsave(&mtk_musb->lock, flags);
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#endif
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if (unlikely(low_power_timer_irq_ctrl))
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enable_irq(mtk_musb->nIrq);
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low_power_timer_wake_cnt++;
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low_power_timer_total_wake_cnt++;
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ktime_wake = ktime_get();
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low_power_timer_total_sleep +=
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ktime_to_us(ktime_sub(ktime_wake, ktime_sleep));
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/* deep idle forbidd here */
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if (low_power_timer_mode == 1)
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usb_hal_dpidle_request(USB_DPIDLE_FORBIDDEN);
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/* make sure all global status sync to memory */
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mb();
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if (low_power_timer_trigger_cnt >= 2) {
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static DEFINE_RATELIMIT_STATE(ratelimit, HZ, 1);
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if (__ratelimit(&ratelimit))
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pr_debug("<ratelimit> avg sleep(%lu/%d, %lu)us,
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avg wake(%lu/%d, %lu)us, mode<%d,%d>,
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local balanced<%d,%d>\n"
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, low_power_timer_total_sleep,
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low_power_timer_trigger_cnt,
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low_power_timer_total_sleep/
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low_power_timer_trigger_cnt,
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low_power_timer_total_wake,
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(low_power_timer_trigger_cnt - 1),
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low_power_timer_total_wake/
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(low_power_timer_trigger_cnt - 1),
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low_power_timer_mode,
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low_power_timer_mode2_option,
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low_power_timer_trigger_cnt,
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low_power_timer_wake_cnt);
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}
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low_power_timer_activate = 0;
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DBG(1, "sleep forbidden <%d,%d>\n",
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low_power_timer_total_trigger_cnt,
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low_power_timer_total_wake_cnt);
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#ifdef TIMER_FUNC_LOCK
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spin_unlock_irqrestore(&mtk_musb->lock, flags);
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#endif
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}
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static void try_trigger_low_power_timer(signed int sleep_ms)
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{
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DBG(1, "sleep_ms:%d\n", sleep_ms);
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if (sleep_ms <= LOW_POWER_TIMER_MIN_PERIOD ||
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sleep_ms >= LOW_POWER_TIMER_MAX_PERIOD) {
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low_power_timer_activate = 0;
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return;
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}
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/* dynamic allocation for timer , result in memory leak */
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#ifdef TIMER_DYNAMIC
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{
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struct timer_list *timer;
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timer = kzalloc(sizeof(struct timer_list), GFP_ATOMIC);
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if (!timer) {
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low_power_timer_activate = 0;
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DBG(0, "alloc timer fail\n");
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return;
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}
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timer_setup(timer, low_power_timer_wakeup_func, 0);
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timer->expires = jiffies + msecs_to_jiffies(sleep_ms);
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add_timer(timer);
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}
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#else
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mod_timer(&low_power_timer, jiffies + msecs_to_jiffies(sleep_ms));
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#endif
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DBG(1, "sleep allowed <%d,%d>, %d ms\n",
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low_power_timer_total_trigger_cnt,
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low_power_timer_total_wake_cnt, sleep_ms);
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ktime_sleep = ktime_get();
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low_power_timer_trigger_cnt++;
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low_power_timer_total_trigger_cnt++;
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if (unlikely(low_power_timer_irq_ctrl))
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disable_irq_nosync(mtk_musb->nIrq);
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if (low_power_timer_trigger_cnt >= 2)
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low_power_timer_total_wake +=
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ktime_to_us(ktime_sub(ktime_sleep, ktime_wake));
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/* deep idle allow here */
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if (low_power_timer_mode == 1)
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usb_hal_dpidle_request(USB_DPIDLE_SRAM);
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}
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static void do_low_power_timer_test_work(struct work_struct *work)
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{
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unsigned long flags;
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signed int set_time;
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unsigned long diff_time_ns;
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int gpd_free_count_last, gpd_free_count;
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int done = 0;
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spin_lock_irqsave(&mtk_musb->lock, flags);
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gpd_free_count = qmu_free_gpd_count(0, ISOC_EP_START_IDX);
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gpd_free_count_last = gpd_free_count;
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spin_unlock_irqrestore(&mtk_musb->lock, flags);
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while (!done) {
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udelay(300);
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spin_lock_irqsave(&mtk_musb->lock, flags);
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gpd_free_count = qmu_free_gpd_count(0, ISOC_EP_START_IDX);
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if (gpd_free_count == gpd_free_count_last) {
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ktime_end = ktime_get();
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diff_time_ns =
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ktime_to_us(ktime_sub(ktime_end, ktime_begin));
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set_time = (low_power_timer_request_time -
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(diff_time_ns/1000));
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try_trigger_low_power_timer(set_time);
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done = 1;
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}
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gpd_free_count_last = gpd_free_count;
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spin_unlock_irqrestore(&mtk_musb->lock, flags);
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}
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}
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static void lower_power_timer_test_init(void)
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{
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INIT_WORK(&low_power_timer_test_work, do_low_power_timer_test_work);
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low_power_timer_test_wq =
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create_singlethread_workqueue("usb20_low_power_timer_test_wq");
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/* TIMER_DEFERRABLE for not interfering with deep idle */
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INIT_DEFERRABLE_WORK(&low_power_timer_montior_work,
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do_low_power_timer_monitor_work);
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schedule_delayed_work(&low_power_timer_montior_work, 0);
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}
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/* mode 0 : no timer mechanism
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* mode 1 : real case for idle task, no-usb-irq control
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* mode 2 + option 0: simulate SCREEN ON mode 1 case
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* mode 2 + option 1: simulate SCREEN OFF mode 1 perfect case
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* mode 2 + option 2: simulate SCREEN OFF mode 1 real case
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*/
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static void low_power_timer_sleep(unsigned int sleep_ms)
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{
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DBG(1, "sleep(%d) ms\n", sleep_ms);
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low_power_timer_activate = 1;
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if (low_power_timer_mode == 2 && low_power_timer_mode2_option != 0)
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low_power_timer_irq_ctrl = 1;
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else
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low_power_timer_irq_ctrl = 0;
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if ((low_power_timer_mode == 2) &&
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(low_power_timer_mode2_option == 2)) {
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low_power_timer_request_time = sleep_ms;
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ktime_begin = ktime_get();
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queue_work(low_power_timer_test_wq, &low_power_timer_test_work);
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} else
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try_trigger_low_power_timer(sleep_ms);
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}
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#endif
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static void mtk_host_active_dev_resource_reset(void)
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{
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memset(mtk_host_active_dev_table, 0, sizeof(mtk_host_active_dev_table));
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mtk_host_active_dev_cnt = 0;
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}
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void musb_host_active_dev_add(unsigned int addr)
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{
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DBG(1, "devnum:%d\n", addr);
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if (addr < MTK_HOST_ACTIVE_DEV_TABLE_SZ &&
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!mtk_host_active_dev_table[addr]) {
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mtk_host_active_dev_table[addr] = 1;
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mtk_host_active_dev_cnt++;
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}
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}
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EXPORT_SYMBOL(musb_host_active_dev_add);
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void __iomem *qmu_base;
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/* debug variable to check qmu_base issue */
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void __iomem *qmu_base_2;
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int musb_qmu_init(struct musb *musb)
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{
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/* set DMA channel 0 burst mode to boost QMU speed */
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musb_writel(musb->mregs, 0x204, musb_readl(musb->mregs, 0x204) | 0x600);
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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/* eanble DMA channel 0 36-BIT support */
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musb_writel(musb->mregs, 0x204,
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musb_readl(musb->mregs, 0x204) | 0x4000);
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#endif
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/* make IOC field in GPD workable */
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musb_writel((musb->mregs + MUSB_QISAR), 0x30, 0);
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qmu_base = (void __iomem *)(mtk_musb->mregs + MUSB_QMUBASE);
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/* debug variable to check qmu_base issue */
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qmu_base_2 = (void __iomem *)(mtk_musb->mregs + MUSB_QMUBASE);
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/* finish all hw op before init qmu */
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mb();
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if (qmu_init_gpd_pool(musb->controller)) {
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QMU_ERR("[QMU]qmu_init_gpd_pool fail\n");
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return -1;
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}
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#ifdef CONFIG_MTK_UAC_POWER_SAVING
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lower_power_timer_test_init();
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#endif
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return 0;
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}
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EXPORT_SYMBOL(musb_qmu_init);
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void musb_qmu_exit(struct musb *musb)
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{
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qmu_destroy_gpd_pool(musb->controller);
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}
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EXPORT_SYMBOL(musb_qmu_exit);
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void musb_disable_q_all(struct musb *musb)
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{
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u32 ep_num;
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QMU_WARN("disable_q_all\n");
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mtk_host_active_dev_resource_reset();
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#ifdef CONFIG_MTK_UAC_POWER_SAVING
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low_power_timer_resource_reset();
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#endif
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for (ep_num = 1; ep_num <= RXQ_NUM; ep_num++) {
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if (mtk_is_qmu_enabled(ep_num, RXQ))
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mtk_disable_q(musb, ep_num, 1);
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/* reset statistics */
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host_qmu_rx_max_active_isoc_gpd[ep_num] = 0;
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host_qmu_rx_max_number_of_pkts[ep_num] = 0;
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}
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for (ep_num = 1; ep_num <= TXQ_NUM; ep_num++) {
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if (mtk_is_qmu_enabled(ep_num, TXQ))
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mtk_disable_q(musb, ep_num, 0);
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/* reset statistics */
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host_qmu_tx_max_active_isoc_gpd[ep_num] = 0;
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host_qmu_tx_max_number_of_pkts[ep_num] = 0;
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}
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}
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EXPORT_SYMBOL(musb_disable_q_all);
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void musb_kick_D_CmdQ(struct musb *musb, struct musb_request *request)
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{
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int isRx;
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isRx = request->tx ? 0 : 1;
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/* enable qmu at musb_gadget_eanble */
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#ifdef NEVER
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if (!mtk_is_qmu_enabled(request->epnum, isRx)) {
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/* enable qmu */
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mtk_qmu_enable(musb, request->epnum, isRx);
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}
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#endif
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/* note tx needed additional zlp field */
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mtk_qmu_insert_task(request->epnum,
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isRx,
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request->request.dma,
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request->request.length,
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((request->request.zero == 1) ? 1 : 0), 1);
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mtk_qmu_resume(request->epnum, isRx);
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}
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EXPORT_SYMBOL(musb_kick_D_CmdQ);
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irqreturn_t musb_q_irq(struct musb *musb)
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{
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irqreturn_t retval = IRQ_NONE;
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u32 wQmuVal = musb->int_queue;
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int i;
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QMU_INFO("wQmuVal:%d\n", wQmuVal);
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for (i = 1; i <= MAX_QMU_EP; i++) {
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if (wQmuVal & DQMU_M_RX_DONE(i)) {
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if (!musb->is_host)
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qmu_done_rx(musb, i);
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else
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h_qmu_done_rx(musb, i);
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}
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if (wQmuVal & DQMU_M_TX_DONE(i)) {
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if (!musb->is_host)
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qmu_done_tx(musb, i);
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else
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h_qmu_done_tx(musb, i);
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}
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}
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mtk_qmu_irq_err(musb, wQmuVal);
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return retval;
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}
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EXPORT_SYMBOL(musb_q_irq);
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void musb_flush_qmu(u32 ep_num, u8 isRx)
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{
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QMU_DBG("flush %s(%d)\n", isRx ? "RQ" : "TQ", ep_num);
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mtk_qmu_stop(ep_num, isRx);
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qmu_reset_gpd_pool(ep_num, isRx);
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}
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EXPORT_SYMBOL(musb_flush_qmu);
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void musb_restart_qmu(struct musb *musb, u32 ep_num, u8 isRx)
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{
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QMU_DBG("restart %s(%d)\n", isRx ? "RQ" : "TQ", ep_num);
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flush_ep_csr(musb, ep_num, isRx);
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mtk_qmu_enable(musb, ep_num, isRx);
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}
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EXPORT_SYMBOL(musb_restart_qmu);
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bool musb_is_qmu_stop(u32 ep_num, u8 isRx)
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{
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void __iomem *base = qmu_base;
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/* debug variable to check qmu_base issue */
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if (qmu_base != qmu_base_2)
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QMU_WARN("qmu_base != qmu_base_2, qmu_base = %p, qmu_base_2=%p"
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, qmu_base, qmu_base_2);
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if (!isRx) {
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if (MGC_ReadQMU16(base, MGC_O_QMU_TQCSR(ep_num))
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& DQMU_QUE_ACTIVE)
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return false;
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else
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return true;
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} else {
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if (MGC_ReadQMU16(base, MGC_O_QMU_RQCSR(ep_num))
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& DQMU_QUE_ACTIVE)
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return false;
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else
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return true;
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}
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}
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#ifndef CONFIG_MTK_MUSB_QMU_PURE_ZLP_SUPPORT
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void musb_tx_zlp_qmu(struct musb *musb, u32 ep_num)
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{
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/* sent ZLP through PIO */
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void __iomem *epio = musb->endpoints[ep_num].regs;
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void __iomem *mbase = musb->mregs;
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int cnt = 50; /* 50*200us, total 10 ms */
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int is_timeout = 1;
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u16 csr;
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QMU_WARN("TX ZLP direct sent\n");
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musb_ep_select(mbase, ep_num);
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/* disable dma for pio */
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csr = musb_readw(epio, MUSB_TXCSR);
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csr &= ~MUSB_TXCSR_DMAENAB;
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musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
/* TXPKTRDY */
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
csr |= MUSB_TXCSR_TXPKTRDY;
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
/* wait ZLP sent */
|
|
while (cnt--) {
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
if (!(csr & MUSB_TXCSR_TXPKTRDY)) {
|
|
is_timeout = 0;
|
|
break;
|
|
}
|
|
udelay(200);
|
|
}
|
|
|
|
/* re-enable dma for qmu */
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
csr |= MUSB_TXCSR_DMAENAB;
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
if (is_timeout)
|
|
QMU_ERR("TX ZLP sent fail???\n");
|
|
QMU_WARN("TX ZLP sent done\n");
|
|
}
|
|
#endif
|
|
|
|
int mtk_kick_CmdQ(struct musb *musb,
|
|
int isRx, struct musb_qh *qh, struct urb *urb)
|
|
{
|
|
void __iomem *mbase = musb->mregs;
|
|
u16 intr_e = 0;
|
|
struct musb_hw_ep *hw_ep = qh->hw_ep;
|
|
void __iomem *epio = hw_ep->regs;
|
|
unsigned int offset = 0;
|
|
u8 bIsIoc;
|
|
dma_addr_t pBuffer;
|
|
u32 dwLength;
|
|
u16 i;
|
|
u32 gpd_free_count = 0;
|
|
|
|
if (!urb) {
|
|
QMU_WARN("!urb\n");
|
|
return -1; /*KOBE : should we return a value */
|
|
}
|
|
|
|
if (!mtk_is_qmu_enabled(hw_ep->epnum, isRx)) {
|
|
DBG(1, "! mtk_is_qmu_enabled<%d,%s>\n",
|
|
hw_ep->epnum, isRx?"RXQ":"TXQ");
|
|
|
|
musb_ep_select(mbase, hw_ep->epnum);
|
|
flush_ep_csr(musb, hw_ep->epnum, isRx);
|
|
|
|
if (isRx) {
|
|
DBG(4, "isRX = 1\n");
|
|
if (qh->type == USB_ENDPOINT_XFER_ISOC) {
|
|
DBG(4, "USB_ENDPOINT_XFER_ISOC\n");
|
|
if (qh->hb_mult == 3)
|
|
musb_writew(epio, MUSB_RXMAXP,
|
|
qh->maxpacket|0x1000);
|
|
else if (qh->hb_mult == 2)
|
|
musb_writew(epio, MUSB_RXMAXP,
|
|
qh->maxpacket|0x800);
|
|
else
|
|
musb_writew(epio, MUSB_RXMAXP,
|
|
qh->maxpacket);
|
|
} else {
|
|
DBG(4, "!! USB_ENDPOINT_XFER_ISOC\n");
|
|
musb_writew(epio, MUSB_RXMAXP, qh->maxpacket);
|
|
}
|
|
|
|
musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_DMAENAB);
|
|
/*CC: speed */
|
|
musb_writeb(epio, MUSB_RXTYPE,
|
|
(qh->type_reg | usb_pipeendpoint(urb->pipe)));
|
|
musb_writeb(epio, MUSB_RXINTERVAL, qh->intv_reg);
|
|
#ifdef CONFIG_USB_MTK_HDRC
|
|
if (musb->is_multipoint) {
|
|
DBG(4, "is_multipoint\n");
|
|
musb_write_rxfunaddr(musb->mregs, hw_ep->epnum,
|
|
qh->addr_reg);
|
|
musb_write_rxhubaddr(musb->mregs, hw_ep->epnum,
|
|
qh->h_addr_reg);
|
|
musb_write_rxhubport(musb->mregs, hw_ep->epnum,
|
|
qh->h_port_reg);
|
|
} else {
|
|
DBG(4, "!! is_multipoint\n");
|
|
musb_writeb(musb->mregs, MUSB_FADDR,
|
|
qh->addr_reg);
|
|
}
|
|
#endif
|
|
/*turn off intrRx*/
|
|
intr_e = musb_readw(musb->mregs, MUSB_INTRRXE);
|
|
intr_e = intr_e & (~(1<<(hw_ep->epnum)));
|
|
musb_writew(musb->mregs, MUSB_INTRRXE, intr_e);
|
|
} else {
|
|
musb_writew(epio, MUSB_TXMAXP, qh->maxpacket);
|
|
musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_DMAENAB);
|
|
/*CC: speed?*/
|
|
musb_writeb(epio, MUSB_TXTYPE,
|
|
(qh->type_reg | usb_pipeendpoint(urb->pipe)));
|
|
musb_writeb(epio, MUSB_TXINTERVAL,
|
|
qh->intv_reg);
|
|
#ifdef CONFIG_USB_MTK_HDRC
|
|
if (musb->is_multipoint) {
|
|
DBG(4, "is_multipoint\n");
|
|
musb_write_txfunaddr(mbase, hw_ep->epnum,
|
|
qh->addr_reg);
|
|
musb_write_txhubaddr(mbase, hw_ep->epnum,
|
|
qh->h_addr_reg);
|
|
musb_write_txhubport(mbase, hw_ep->epnum,
|
|
qh->h_port_reg);
|
|
/* FIXME if !epnum, do the same for RX ... */
|
|
} else {
|
|
DBG(4, "!! is_multipoint\n");
|
|
musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
|
|
}
|
|
#endif
|
|
/*
|
|
* Turn off intrTx ,
|
|
* but this will be revert
|
|
* by musb_ep_program
|
|
*/
|
|
intr_e = musb_readw(musb->mregs, MUSB_INTRTXE);
|
|
intr_e = intr_e & (~(1<<hw_ep->epnum));
|
|
musb_writew(musb->mregs, MUSB_INTRTXE, intr_e);
|
|
}
|
|
|
|
mtk_qmu_enable(musb, hw_ep->epnum, isRx);
|
|
}
|
|
|
|
gpd_free_count = qmu_free_gpd_count(isRx, hw_ep->epnum);
|
|
if (qh->type == USB_ENDPOINT_XFER_ISOC) {
|
|
u32 gpd_used_count;
|
|
|
|
DBG(4, "USB_ENDPOINT_XFER_ISOC\n");
|
|
pBuffer = urb->transfer_dma;
|
|
|
|
if (gpd_free_count < urb->number_of_packets) {
|
|
DBG(0, "gpd_free_count:%d, number_of_packets:%d\n",
|
|
gpd_free_count, urb->number_of_packets);
|
|
DBG(0, "%s:%d Error Here\n", __func__, __LINE__);
|
|
return -ENOSPC;
|
|
}
|
|
for (i = 0; i < urb->number_of_packets; i++) {
|
|
urb->iso_frame_desc[i].status = 0;
|
|
offset = urb->iso_frame_desc[i].offset;
|
|
dwLength = urb->iso_frame_desc[i].length;
|
|
/* If interrupt on complete ? */
|
|
bIsIoc = (i == (urb->number_of_packets-1)) ? 1 : 0;
|
|
DBG(4, "mtk_qmu_insert_task\n");
|
|
mtk_qmu_insert_task(hw_ep->epnum, isRx,
|
|
pBuffer + offset, dwLength, 0, bIsIoc);
|
|
|
|
mtk_qmu_resume(hw_ep->epnum, isRx);
|
|
}
|
|
|
|
gpd_used_count = qmu_used_gpd_count(isRx, hw_ep->epnum);
|
|
|
|
if (!isRx) {
|
|
if (host_qmu_tx_max_active_isoc_gpd[hw_ep->epnum]
|
|
< gpd_used_count)
|
|
|
|
host_qmu_tx_max_active_isoc_gpd[hw_ep->epnum]
|
|
= gpd_used_count;
|
|
|
|
if (host_qmu_tx_max_number_of_pkts[hw_ep->epnum]
|
|
< urb->number_of_packets)
|
|
|
|
host_qmu_tx_max_number_of_pkts[hw_ep->epnum]
|
|
= urb->number_of_packets;
|
|
|
|
DBG_LIMIT(1,
|
|
"TXQ[%d], max_isoc gpd:%d, max_pkts:%d, active_dev:%d\n",
|
|
hw_ep->epnum,
|
|
host_qmu_tx_max_active_isoc_gpd
|
|
[hw_ep->epnum],
|
|
host_qmu_tx_max_number_of_pkts
|
|
[hw_ep->epnum],
|
|
mtk_host_active_dev_cnt);
|
|
|
|
#ifdef CONFIG_MTK_UAC_POWER_SAVING
|
|
DBG(1,
|
|
"mode:%d, activate:%d, ep:%d-%s, mtk_host_active_dev_cnt:%d\n",
|
|
low_power_timer_mode,
|
|
low_power_timer_activate,
|
|
hw_ep->epnum, isRx?"in":"out",
|
|
mtk_host_active_dev_cnt);
|
|
if (low_power_timer_mode
|
|
&& !low_power_timer_activate
|
|
&& mtk_host_active_dev_cnt == 1
|
|
&& hw_ep->epnum == ISOC_EP_START_IDX
|
|
&& usb_on_sram
|
|
&& audio_on_sram
|
|
&& (host_qmu_rx_max_active_isoc_gpd
|
|
[ISOC_EP_START_IDX] == 0)) {
|
|
if (urb->dev->speed == USB_SPEED_FULL)
|
|
low_power_timer_sleep
|
|
(gpd_used_count * 3 / 4);
|
|
else
|
|
low_power_timer_sleep
|
|
(gpd_used_count * 2 / 3 / 8);
|
|
}
|
|
#endif
|
|
} else {
|
|
if (host_qmu_rx_max_active_isoc_gpd[hw_ep->epnum]
|
|
< gpd_used_count)
|
|
|
|
host_qmu_rx_max_active_isoc_gpd[hw_ep->epnum]
|
|
= gpd_used_count;
|
|
|
|
if (host_qmu_rx_max_number_of_pkts[hw_ep->epnum]
|
|
< urb->number_of_packets)
|
|
|
|
host_qmu_rx_max_number_of_pkts[hw_ep->epnum]
|
|
= urb->number_of_packets;
|
|
|
|
DBG_LIMIT(1,
|
|
"RXQ[%d], max_isoc gpd:%d, max_pkts:%d, active_dev:%d\n",
|
|
hw_ep->epnum,
|
|
host_qmu_rx_max_active_isoc_gpd
|
|
[hw_ep->epnum],
|
|
host_qmu_rx_max_number_of_pkts
|
|
[hw_ep->epnum],
|
|
mtk_host_active_dev_cnt);
|
|
}
|
|
} else {
|
|
/* Must be the bulk transfer type */
|
|
QMU_WARN("non isoc\n");
|
|
pBuffer = urb->transfer_dma;
|
|
if (urb->transfer_buffer_length < QMU_RX_SPLIT_THRE) {
|
|
if (gpd_free_count < 1) {
|
|
DBG(0,
|
|
"gpd_free_count:%d, number_of_packets:%d\n",
|
|
gpd_free_count, urb->number_of_packets);
|
|
DBG(0, "%s:%d Error Here\n",
|
|
__func__, __LINE__);
|
|
return -ENOSPC;
|
|
}
|
|
DBG(4, "urb->transfer_buffer_length : %d\n",
|
|
urb->transfer_buffer_length);
|
|
|
|
dwLength = urb->transfer_buffer_length;
|
|
bIsIoc = 1;
|
|
|
|
mtk_qmu_insert_task(hw_ep->epnum, isRx,
|
|
pBuffer + offset, dwLength, 0, bIsIoc);
|
|
mtk_qmu_resume(hw_ep->epnum, isRx);
|
|
} else {
|
|
/*reuse isoc urb->unmber_of_packets*/
|
|
urb->number_of_packets =
|
|
((urb->transfer_buffer_length)
|
|
+ QMU_RX_SPLIT_BLOCK_SIZE-1)
|
|
/(QMU_RX_SPLIT_BLOCK_SIZE);
|
|
if (gpd_free_count < urb->number_of_packets) {
|
|
DBG(0,
|
|
"gpd_free_count:%d, number_of_packets:%d\n",
|
|
gpd_free_count, urb->number_of_packets);
|
|
DBG(0, "%s:%d Error Here\n"
|
|
, __func__, __LINE__);
|
|
return -ENOSPC;
|
|
}
|
|
for (i = 0; i < urb->number_of_packets; i++) {
|
|
offset = QMU_RX_SPLIT_BLOCK_SIZE*i;
|
|
dwLength = QMU_RX_SPLIT_BLOCK_SIZE;
|
|
|
|
/* If interrupt on complete ? */
|
|
bIsIoc = (i == (urb->number_of_packets-1)) ?
|
|
1 : 0;
|
|
dwLength = (i == (urb->number_of_packets-1)) ?
|
|
((urb->transfer_buffer_length)
|
|
% QMU_RX_SPLIT_BLOCK_SIZE) : dwLength;
|
|
if (dwLength == 0)
|
|
dwLength = QMU_RX_SPLIT_BLOCK_SIZE;
|
|
|
|
mtk_qmu_insert_task(hw_ep->epnum, isRx,
|
|
pBuffer + offset, dwLength, 0, bIsIoc);
|
|
mtk_qmu_resume(hw_ep->epnum, isRx);
|
|
}
|
|
}
|
|
}
|
|
/*sync register*/
|
|
mb();
|
|
|
|
DBG(4, "\n");
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(mtk_kick_CmdQ);
|