4589 lines
327 KiB
C
4589 lines
327 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_MT6382_H
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#define _MTK_MT6382_H
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//------------------------------------------------------------------------
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// RX register map
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//------------------------------------------------------------------------
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#define MIPI_RX_PHY_BASE 0x00040000
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#define PPI_STARTUP_RW_COMMON_DPHY_0 0xc00
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#define PPI_STARTUP_RW_COMMON_DPHY_1 0xc01
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#define PPI_STARTUP_RW_COMMON_DPHY_2 0xc02
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#define PPI_STARTUP_RW_COMMON_DPHY_3 0xc03
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#define PPI_STARTUP_RW_COMMON_DPHY_4 0xc04
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#define PPI_STARTUP_RW_COMMON_DPHY_5 0xc05
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#define PPI_STARTUP_RW_COMMON_DPHY_6 0xc06
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#define PPI_STARTUP_RW_COMMON_DPHY_7 0xc07
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#define PPI_STARTUP_RW_COMMON_DPHY_8 0xc08
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#define PPI_STARTUP_RW_COMMON_DPHY_9 0xc09
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#define PPI_STARTUP_RW_COMMON_DPHY_A 0xc0a
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#define PPI_STARTUP_RW_COMMON_DPHY_10 0xc10
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#define PPI_STARTUP_RW_COMMON_STARTUP_1_1 0xc11
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0 0xc20
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_1 0xc21
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_2 0xc22
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_3 0xc23
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_4 0xc24
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5 0xc25
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#define PPI_CALIBCTRL_RW_COMMON_BG_0 0xc26
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_7 0xc27
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#define PPI_CALIBCTRL_RW_ADC_CFG_0 0xc28
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#define PPI_CALIBCTRL_RW_ADC_CFG_1 0xc29
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#define PPI_CALIBCTRL_R_ADC_DEBUG 0xc2a
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE 0xe00
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#define PPI_RW_LPDCOCAL_TIMEBASE 0xe01
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#define PPI_RW_LPDCOCAL_NREF 0xe02
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#define PPI_RW_LPDCOCAL_NREF_RANGE 0xe03
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#define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN 0xe04
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#define PPI_RW_LPDCOCAL_TWAIT_CONFIG 0xe05
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#define PPI_RW_LPDCOCAL_VT_CONFIG 0xe06
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#define PPI_R_LPDCOCAL_DEBUG_RB 0xe07
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#define PPI_RW_LPDCOCAL_COARSE_CFG 0xe08
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_RB 0xe09
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_0_RB 0xe0a
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_1_RB 0xe0b
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_FWORD_RB 0xe0c
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_CURR_ERROR 0xe0d
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_LAST_ERROR 0xe0e
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#define PPI_R_LPDCOCAL_DEBUG_VT 0xe0f
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#define PPI_RW_LB_TIMEBASE_CONFIG 0xe10
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#define PPI_RW_LB_STARTCMU_CONFIG 0xe11
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#define PPI_R_LBPULSE_COUNTER_RB 0xe12
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#define PPI_R_LB_START_CMU_RB 0xe13
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#define PPI_RW_LB_DPHY_BURST_START 0xe14
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#define PPI_RW_LB_CPHY_BURST_START 0xe15
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#define PPI_RW_DDLCAL_CFG_0 0xe20
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#define PPI_RW_DDLCAL_CFG_1 0xe21
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#define PPI_RW_DDLCAL_CFG_2 0xe22
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#define PPI_RW_DDLCAL_CFG_3 0xe23
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#define PPI_RW_DDLCAL_CFG_4 0xe24
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#define PPI_RW_DDLCAL_CFG_5 0xe25
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#define PPI_RW_DDLCAL_CFG_6 0xe26
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#define PPI_RW_DDLCAL_CFG_7 0xe27
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#define PPI_R_DDLCAL_DEBUG_0 0xe28
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#define PPI_R_DDLCAL_DEBUG_1 0xe28
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#define PPI_RW_PARITY_TEST 0xe30
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#define PPI_RW_STARTUP_OVR_0 0xe31
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#define PPI_RW_STARTUP_STATE_OVR_1 0xe32
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#define PPI_RW_DTB_SELECTOR 0xe33
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#define PPI_RW_DPHY_CLK_SPARE 0xe35
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#define PPI_RW_COMMON_CFG 0xe36
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#define PPI_RW_TERMCAL_CFG_0 0xe40
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#define PPI_R_TERMCAL_DEBUG_0 0xe41
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#define PPI_RW_OFFSETCAL_CFG_0 0xe50
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#define PPI_R_OFFSETCAL_DEBUG_LANE0 0xe51
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#define PPI_R_OFFSETCAL_DEBUG_LANE1 0xe52
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#define PPI_R_OFFSETCAL_DEBUG_LANE2 0xe53
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#define PPI_R_OFFSETCAL_DEBUG_LANE3 0xe54
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#define PPI_R_OFFSETCAL_DEBUG_LANE4 0xe55
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1 0x1001
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2 0x1002
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3 0x1003
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4 0x1004
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5 0x1005
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6 0x1006
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7 0x1007
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8 0x1008
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9 0x1009
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10 0x100a
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11 0x100b
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_12 0x100c
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13 0x100d
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14 0x100e
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15 0x100f
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_0 0x1010
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1 0x1011
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2 0x1012
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_3 0x1013
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4 0x1014
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5 0x1015
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6 0x1016
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7 0x1017
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8 0x1018
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9 0x1019
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_10 0x101a
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11 0x101b
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12 0x101c
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_13 0x101d
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14 0x101e
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15 0x101f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_0 0x1020
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_1 0x1021
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2 0x1022
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3 0x1023
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4 0x1024
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5 0x1025
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6 0x1026
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7 0x1027
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8 0x1028
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9 0x1029
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10 0x102a
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11 0x102b
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12 0x102c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13 0x102d
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14 0x102e
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15 0x102f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_0 0x1030
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_1 0x1031
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2 0x1032
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_3 0x1033
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4 0x1034
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5 0x1035
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6 0x1036
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7 0x1037
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8 0x1038
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9 0x1039
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_10 0x103a
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11 0x103b
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12 0x103c
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13 0x103d
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14 0x103e
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_15 0x103f
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_0 0x1040
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1 0x1041
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_2 0x1042
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3 0x1043
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4 0x1044
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0 0x1050
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_1 0x1051
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2 0x1052
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3 0x1053
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4 0x1054
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#define CORE_DIG_RW_TRIO0_0 0x1080
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#define CORE_DIG_RW_TRIO0_1 0x1081
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#define CORE_DIG_RW_TRIO0_2 0x1082
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0 0x1200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1 0x1201
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2 0x1202
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3 0x1203
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4 0x1204
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5 0x1205
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6 0x1206
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7 0x1207
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8 0x1208
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9 0x1209
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10 0x120a
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11 0x120b
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_12 0x120c
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13 0x120d
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14 0x120e
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15 0x120f
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_0 0x1210
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1 0x1211
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2 0x1212
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_3 0x1213
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4 0x1214
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5 0x1215
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6 0x1216
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7 0x1217
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8 0x1218
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9 0x1219
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_10 0x121a
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11 0x121b
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12 0x121c
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_13 0x121d
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14 0x121e
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15 0x121f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_0 0x1220
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_1 0x1221
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2 0x1222
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3 0x1223
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4 0x1224
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5 0x1225
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6 0x1226
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7 0x1227
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8 0x1228
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9 0x1229
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10 0x122a
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11 0x122b
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12 0x122c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13 0x122d
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14 0x122e
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15 0x122f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_0 0x1230
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_1 0x1231
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2 0x1232
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_3 0x1233
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4 0x1234
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5 0x1235
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6 0x1236
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7 0x1237
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8 0x1238
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9 0x1239
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_10 0x123a
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11 0x123b
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12 0x123c
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13 0x123d
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14 0x123e
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_15 0x123f
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_0 0x1240
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1 0x1241
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_2 0x1242
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3 0x1243
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4 0x1244
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0 0x1250
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_1 0x1251
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2 0x1252
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3 0x1253
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4 0x1254
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#define CORE_DIG_RW_TRIO1_0 0x1280
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#define CORE_DIG_RW_TRIO1_1 0x1281
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#define CORE_DIG_RW_TRIO1_2 0x1282
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0 0x1400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1 0x1401
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2 0x1402
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3 0x1403
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4 0x1404
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5 0x1405
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6 0x1406
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7 0x1407
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8 0x1408
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9 0x1409
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10 0x140a
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11 0x140b
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_12 0x140c
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13 0x140d
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14 0x140e
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15 0x140f
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_0 0x1410
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1 0x1411
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2 0x1412
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_3 0x1413
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4 0x1414
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5 0x1415
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6 0x1416
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7 0x1417
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8 0x1418
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9 0x1419
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_10 0x141a
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11 0x141b
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12 0x141c
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_13 0x141d
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14 0x141e
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15 0x141f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_0 0x1420
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_1 0x1421
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2 0x1422
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3 0x1423
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4 0x1424
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5 0x1425
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6 0x1426
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7 0x1427
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8 0x1428
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9 0x1429
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10 0x142a
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11 0x142b
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12 0x142c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13 0x142d
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14 0x142e
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15 0x142f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_0 0x1430
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_1 0x1431
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2 0x1432
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_3 0x1433
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4 0x1434
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5 0x1435
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6 0x1436
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7 0x1437
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8 0x1438
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9 0x1439
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_10 0x143a
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11 0x143b
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12 0x143c
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13 0x143d
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14 0x143e
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_15 0x143f
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_0 0x1440
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1 0x1441
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_2 0x1442
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3 0x1443
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4 0x1444
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0 0x1450
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_1 0x1451
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2 0x1452
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3 0x1453
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4 0x1454
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#define CORE_DIG_RW_TRIO2_0 0x1480
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#define CORE_DIG_RW_TRIO2_1 0x1481
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#define CORE_DIG_RW_TRIO2_2 0x1482
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0 0x1600
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1 0x1601
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2 0x1602
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3 0x1603
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4 0x1604
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5 0x1605
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6 0x1606
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7 0x1607
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8 0x1608
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9 0x1609
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10 0x160a
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11 0x160b
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_12 0x160c
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13 0x160d
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14 0x160e
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15 0x160f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_0 0x1620
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_1 0x1621
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2 0x1622
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3 0x1623
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4 0x1624
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5 0x1625
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6 0x1626
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7 0x1627
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8 0x1628
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9 0x1629
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10 0x162a
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11 0x162b
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12 0x162c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13 0x162d
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14 0x162e
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15 0x162f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_0 0x1630
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_1 0x1631
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2 0x1632
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_3 0x1633
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4 0x1634
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5 0x1635
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6 0x1636
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7 0x1637
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8 0x1638
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9 0x1639
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_10 0x163a
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11 0x163b
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12 0x163c
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13 0x163d
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14 0x163e
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_15 0x163f
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_0 0x1640
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1 0x1641
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_2 0x1642
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3 0x1643
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4 0x1644
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_0 0x1820
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_1 0x1821
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2 0x1822
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3 0x1823
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4 0x1824
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5 0x1825
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6 0x1826
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7 0x1827
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8 0x1828
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9 0x1829
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10 0x182a
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11 0x182b
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12 0x182c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13 0x182d
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14 0x182e
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15 0x182f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_0 0x1830
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_1 0x1831
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2 0x1832
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_3 0x1833
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4 0x1834
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5 0x1835
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6 0x1836
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7 0x1837
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8 0x1838
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9 0x1839
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_10 0x183a
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11 0x183b
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12 0x183c
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13 0x183d
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14 0x183e
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_15 0x183f
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_0 0x1840
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1 0x1841
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_2 0x1842
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3 0x1843
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4 0x1844
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0 0x1a00
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1 0x1a01
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2 0x1a02
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0 0x1c00
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1 0x1c01
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_2 0x1c02
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_3 0x1c03
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_4 0x1c04
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_5 0x1c05
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_6 0x1c06
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_7 0x1c07
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_8 0x1c08
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_9 0x1c09
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_10 0x1c0a
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11 0x1c0b
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_12 0x1c0c
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_13 0x1c0d
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_14 0x1c0e
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_15 0x1c0f
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_0 0x1c10
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_1 0x1c11
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_2 0x1c12
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_3 0x1c13
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_4 0x1c14
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0 0x1c20
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1 0x1c21
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2 0x1c22
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3 0x1c23
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4 0x1c24
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5 0x1c25
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6 0x1c26
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7 0x1c27
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8 0x1c28
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9 0x1c29
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10 0x1c2a
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_11 0x1c2b
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12 0x1c2c
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13 0x1c2d
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14 0x1c2e
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15 0x1c2f
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0 0x1c30
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#define CORE_DIG_RW_COMMON_0 0x1c40
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#define CORE_DIG_RW_COMMON_1 0x1c41
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#define CORE_DIG_RW_COMMON_2 0x1c42
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#define CORE_DIG_RW_COMMON_3 0x1c43
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#define CORE_DIG_RW_COMMON_4 0x1c44
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#define CORE_DIG_RW_COMMON_5 0x1c45
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#define CORE_DIG_RW_COMMON_6 0x1c46
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#define CORE_DIG_RW_COMMON_7 0x1c47
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#define CORE_DIG_RW_COMMON_8 0x1c48
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#define CORE_DIG_RW_COMMON_9 0x1c49
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#define CORE_DIG_RW_COMMON_10 0x1c4a
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#define CORE_DIG_RW_COMMON_11 0x1c4b
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#define CORE_DIG_RW_COMMON_12 0x1c4c
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#define CORE_DIG_RW_COMMON_13 0x1c4d
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#define CORE_DIG_RW_COMMON_14 0x1c4e
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#define CORE_DIG_RW_COMMON_15 0x1c4f
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0 0x1cf0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_1 0x1cf1
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2 0x1cf2
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_3 0x1cf3
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#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM 0x1ff0
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#define CORE_DIG_COMMON_R_DESKEW_FINE_MEM 0x1ff1
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#define PPI_RW_DPHY_LANE0_LBERT_0 0x2000
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#define PPI_RW_DPHY_LANE0_LBERT_1 0x2001
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#define PPI_R_DPHY_LANE0_LBERT_0 0x2002
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#define PPI_R_DPHY_LANE0_LBERT_1 0x2003
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#define PPI_RW_DPHY_LANE0_SPARE 0x2004
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#define PPI_RW_DPHY_LANE1_LBERT_0 0x2200
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#define PPI_RW_DPHY_LANE1_LBERT_1 0x2201
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#define PPI_R_DPHY_LANE1_LBERT_0 0x2202
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#define PPI_R_DPHY_LANE1_LBERT_1 0x2203
|
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#define PPI_RW_DPHY_LANE1_SPARE 0x2204
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#define PPI_RW_DPHY_LANE2_LBERT_0 0x2400
|
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#define PPI_RW_DPHY_LANE2_LBERT_1 0x2401
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#define PPI_R_DPHY_LANE2_LBERT_0 0x2402
|
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#define PPI_R_DPHY_LANE2_LBERT_1 0x2403
|
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#define PPI_RW_DPHY_LANE2_SPARE 0x2404
|
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#define PPI_RW_DPHY_LANE3_LBERT_0 0x2600
|
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#define PPI_RW_DPHY_LANE3_LBERT_1 0x2601
|
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#define PPI_R_DPHY_LANE3_LBERT_0 0x2602
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#define PPI_R_DPHY_LANE3_LBERT_1 0x2603
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#define PPI_RW_DPHY_LANE3_SPARE 0x2604
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#define CORE_DIG_DLANE_0_RW_CFG_0 0x3000
|
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#define CORE_DIG_DLANE_0_RW_CFG_1 0x3001
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#define CORE_DIG_DLANE_0_RW_CFG_2 0x3002
|
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#define CORE_DIG_DLANE_0_RW_LP_0 0x3040
|
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#define CORE_DIG_DLANE_0_RW_LP_1 0x3041
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#define CORE_DIG_DLANE_0_R_LP_0 0x3050
|
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#define CORE_DIG_DLANE_0_R_LP_1 0x3051
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#define CORE_DIG_DLANE_0_R_HS_TX_0 0x3070
|
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#define CORE_DIG_DLANE_0_RW_HS_RX_0 0x3080
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#define CORE_DIG_DLANE_0_RW_HS_RX_1 0x3081
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#define CORE_DIG_DLANE_0_RW_HS_RX_2 0x3082
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#define CORE_DIG_DLANE_0_RW_HS_RX_3 0x3083
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#define CORE_DIG_DLANE_0_RW_HS_RX_4 0x3084
|
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#define CORE_DIG_DLANE_0_RW_HS_RX_5 0x3085
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#define CORE_DIG_DLANE_0_RW_HS_RX_6 0x3086
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#define CORE_DIG_DLANE_0_RW_HS_RX_7 0x3087
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#define CORE_DIG_DLANE_0_RW_HS_RX_8 0x3088
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#define CORE_DIG_DLANE_0_R_HS_RX_0 0x3090
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#define CORE_DIG_DLANE_0_R_HS_RX_1 0x3091
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#define CORE_DIG_DLANE_0_R_HS_RX_2 0x3092
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#define CORE_DIG_DLANE_0_R_HS_RX_3 0x3093
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#define CORE_DIG_DLANE_0_R_HS_RX_4 0x3094
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#define CORE_DIG_DLANE_0_RW_HS_TX_0 0x3100
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#define CORE_DIG_DLANE_0_RW_HS_TX_1 0x3101
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#define CORE_DIG_DLANE_0_RW_HS_TX_2 0x3102
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#define CORE_DIG_DLANE_0_RW_HS_TX_3 0x3103
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#define CORE_DIG_DLANE_0_RW_HS_TX_4 0x3104
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#define CORE_DIG_DLANE_0_RW_HS_TX_5 0x3105
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#define CORE_DIG_DLANE_0_RW_HS_TX_6 0x3106
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#define CORE_DIG_DLANE_0_RW_HS_TX_7 0x3107
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#define CORE_DIG_DLANE_0_RW_HS_TX_8 0x3108
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#define CORE_DIG_DLANE_0_RW_HS_TX_9 0x3109
|
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#define CORE_DIG_DLANE_0_RW_HS_TX_10 0x310a
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#define CORE_DIG_DLANE_0_RW_HS_TX_11 0x310b
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#define CORE_DIG_DLANE_0_RW_HS_TX_12 0x310c
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#define CORE_DIG_DLANE_1_RW_CFG_0 0x3200
|
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#define CORE_DIG_DLANE_1_RW_CFG_1 0x3201
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#define CORE_DIG_DLANE_1_RW_CFG_2 0x3202
|
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#define CORE_DIG_DLANE_1_RW_LP_0 0x3240
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#define CORE_DIG_DLANE_1_RW_LP_1 0x3241
|
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#define CORE_DIG_DLANE_1_R_LP_0 0x3250
|
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#define CORE_DIG_DLANE_1_R_LP_1 0x3251
|
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#define CORE_DIG_DLANE_1_R_HS_TX_0 0x3270
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_0 0x3280
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_1 0x3281
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_2 0x3282
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_3 0x3283
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_4 0x3284
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_5 0x3285
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_6 0x3286
|
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#define CORE_DIG_DLANE_1_RW_HS_RX_7 0x3287
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#define CORE_DIG_DLANE_1_RW_HS_RX_8 0x3288
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#define CORE_DIG_DLANE_1_R_HS_RX_0 0x3290
|
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#define CORE_DIG_DLANE_1_R_HS_RX_1 0x3291
|
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#define CORE_DIG_DLANE_1_R_HS_RX_2 0x3292
|
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#define CORE_DIG_DLANE_1_R_HS_RX_3 0x3293
|
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#define CORE_DIG_DLANE_1_R_HS_RX_4 0x3294
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_0 0x3300
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_1 0x3301
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_2 0x3302
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_3 0x3303
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_4 0x3304
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#define CORE_DIG_DLANE_1_RW_HS_TX_5 0x3305
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_6 0x3306
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_7 0x3307
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#define CORE_DIG_DLANE_1_RW_HS_TX_8 0x3308
|
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#define CORE_DIG_DLANE_1_RW_HS_TX_9 0x3309
|
|
#define CORE_DIG_DLANE_1_RW_HS_TX_10 0x330a
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#define CORE_DIG_DLANE_1_RW_HS_TX_11 0x330b
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#define CORE_DIG_DLANE_1_RW_HS_TX_12 0x330c
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#define CORE_DIG_DLANE_2_RW_CFG_0 0x3400
|
|
#define CORE_DIG_DLANE_2_RW_CFG_1 0x3401
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#define CORE_DIG_DLANE_2_RW_CFG_2 0x3402
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#define CORE_DIG_DLANE_2_RW_LP_0 0x3440
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#define CORE_DIG_DLANE_2_RW_LP_1 0x3441
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#define CORE_DIG_DLANE_2_R_LP_0 0x3450
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#define CORE_DIG_DLANE_2_R_LP_1 0x3451
|
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#define CORE_DIG_DLANE_2_R_HS_TX_0 0x3470
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|
#define CORE_DIG_DLANE_2_RW_HS_RX_0 0x3480
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#define CORE_DIG_DLANE_2_RW_HS_RX_1 0x3481
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#define CORE_DIG_DLANE_2_RW_HS_RX_2 0x3482
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#define CORE_DIG_DLANE_2_RW_HS_RX_3 0x3483
|
|
#define CORE_DIG_DLANE_2_RW_HS_RX_4 0x3484
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#define CORE_DIG_DLANE_2_RW_HS_RX_5 0x3485
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#define CORE_DIG_DLANE_2_RW_HS_RX_6 0x3486
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|
#define CORE_DIG_DLANE_2_RW_HS_RX_7 0x3487
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#define CORE_DIG_DLANE_2_RW_HS_RX_8 0x3488
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|
#define CORE_DIG_DLANE_2_R_HS_RX_0 0x3490
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|
#define CORE_DIG_DLANE_2_R_HS_RX_1 0x3491
|
|
#define CORE_DIG_DLANE_2_R_HS_RX_2 0x3492
|
|
#define CORE_DIG_DLANE_2_R_HS_RX_3 0x3493
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|
#define CORE_DIG_DLANE_2_R_HS_RX_4 0x3494
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#define CORE_DIG_DLANE_2_RW_HS_TX_0 0x3500
|
|
#define CORE_DIG_DLANE_2_RW_HS_TX_1 0x3501
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|
#define CORE_DIG_DLANE_2_RW_HS_TX_2 0x3502
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#define CORE_DIG_DLANE_2_RW_HS_TX_3 0x3503
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|
#define CORE_DIG_DLANE_2_RW_HS_TX_4 0x3504
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|
#define CORE_DIG_DLANE_2_RW_HS_TX_5 0x3505
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|
#define CORE_DIG_DLANE_2_RW_HS_TX_6 0x3506
|
|
#define CORE_DIG_DLANE_2_RW_HS_TX_7 0x3507
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#define CORE_DIG_DLANE_2_RW_HS_TX_8 0x3508
|
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#define CORE_DIG_DLANE_2_RW_HS_TX_9 0x3509
|
|
#define CORE_DIG_DLANE_2_RW_HS_TX_10 0x350a
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#define CORE_DIG_DLANE_2_RW_HS_TX_11 0x350b
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#define CORE_DIG_DLANE_2_RW_HS_TX_12 0x350c
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#define CORE_DIG_DLANE_3_RW_CFG_0 0x3600
|
|
#define CORE_DIG_DLANE_3_RW_CFG_1 0x3601
|
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#define CORE_DIG_DLANE_3_RW_CFG_2 0x3602
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#define CORE_DIG_DLANE_3_RW_LP_0 0x3640
|
|
#define CORE_DIG_DLANE_3_RW_LP_1 0x3641
|
|
#define CORE_DIG_DLANE_3_R_LP_0 0x3650
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#define CORE_DIG_DLANE_3_R_LP_1 0x3651
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#define CORE_DIG_DLANE_3_R_HS_TX_0 0x3670
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#define CORE_DIG_DLANE_3_RW_HS_RX_0 0x3680
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#define CORE_DIG_DLANE_3_RW_HS_RX_1 0x3681
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#define CORE_DIG_DLANE_3_RW_HS_RX_2 0x3682
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#define CORE_DIG_DLANE_3_RW_HS_RX_3 0x3683
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#define CORE_DIG_DLANE_3_RW_HS_RX_4 0x3684
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#define CORE_DIG_DLANE_3_RW_HS_RX_5 0x3685
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#define CORE_DIG_DLANE_3_RW_HS_RX_6 0x3686
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#define CORE_DIG_DLANE_3_RW_HS_RX_7 0x3687
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#define CORE_DIG_DLANE_3_RW_HS_RX_8 0x3688
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#define CORE_DIG_DLANE_3_R_HS_RX_0 0x3690
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|
#define CORE_DIG_DLANE_3_R_HS_RX_1 0x3691
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|
#define CORE_DIG_DLANE_3_R_HS_RX_2 0x3692
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|
#define CORE_DIG_DLANE_3_R_HS_RX_3 0x3693
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|
#define CORE_DIG_DLANE_3_R_HS_RX_4 0x3694
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_0 0x3700
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_1 0x3701
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_2 0x3702
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_3 0x3703
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_4 0x3704
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_5 0x3705
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_6 0x3706
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_7 0x3707
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_8 0x3708
|
|
#define CORE_DIG_DLANE_3_RW_HS_TX_9 0x3709
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|
#define CORE_DIG_DLANE_3_RW_HS_TX_10 0x370a
|
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#define CORE_DIG_DLANE_3_RW_HS_TX_11 0x370b
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#define CORE_DIG_DLANE_3_RW_HS_TX_12 0x370c
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#define CORE_DIG_DLANE_CLK_RW_CFG_0 0x3800
|
|
#define CORE_DIG_DLANE_CLK_RW_CFG_1 0x3801
|
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#define CORE_DIG_DLANE_CLK_RW_CFG_2 0x3802
|
|
#define CORE_DIG_DLANE_CLK_RW_LP_0 0x3840
|
|
#define CORE_DIG_DLANE_CLK_RW_LP_1 0x3841
|
|
#define CORE_DIG_DLANE_CLK_R_LP_0 0x3850
|
|
#define CORE_DIG_DLANE_CLK_R_LP_1 0x3851
|
|
#define CORE_DIG_DLANE_CLK_R_HS_TX_0 0x3870
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_0 0x3880
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_1 0x3881
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_2 0x3882
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_3 0x3883
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_4 0x3884
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_5 0x3885
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_6 0x3886
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_7 0x3887
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_RX_8 0x3888
|
|
#define CORE_DIG_DLANE_CLK_R_HS_RX_0 0x3890
|
|
#define CORE_DIG_DLANE_CLK_R_HS_RX_1 0x3891
|
|
#define CORE_DIG_DLANE_CLK_R_HS_RX_2 0x3892
|
|
#define CORE_DIG_DLANE_CLK_R_HS_RX_3 0x3893
|
|
#define CORE_DIG_DLANE_CLK_R_HS_RX_4 0x3894
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_0 0x3900
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_1 0x3901
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_2 0x3902
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_3 0x3903
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_4 0x3904
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_5 0x3905
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_6 0x3906
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_7 0x3907
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_8 0x3908
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_9 0x3909
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_10 0x390a
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_11 0x390b
|
|
#define CORE_DIG_DLANE_CLK_RW_HS_TX_12 0x390c
|
|
#define PPI_RW_CPHY_TRIO0_LBERT_0 0x4000
|
|
#define PPI_RW_CPHY_TRIO0_LBERT_1 0x4001
|
|
#define PPI_R_CPHY_TRIO0_LBERT_0 0x4002
|
|
#define PPI_R_CPHY_TRIO0_LBERT_1 0x4003
|
|
#define PPI_RW_CPHY_TRIO0_SPARE 0x4004
|
|
#define PPI_RW_CPHY_TRIO1_LBERT_0 0x4200
|
|
#define PPI_RW_CPHY_TRIO1_LBERT_1 0x4201
|
|
#define PPI_R_CPHY_TRIO1_LBERT_0 0x4202
|
|
#define PPI_R_CPHY_TRIO1_LBERT_1 0x4203
|
|
#define PPI_RW_CPHY_TRIO1_SPARE 0x4204
|
|
#define PPI_RW_CPHY_TRIO2_LBERT_0 0x4400
|
|
#define PPI_RW_CPHY_TRIO2_LBERT_1 0x4401
|
|
#define PPI_R_CPHY_TRIO2_LBERT_0 0x4402
|
|
#define PPI_R_CPHY_TRIO2_LBERT_1 0x4403
|
|
#define PPI_RW_CPHY_TRIO2_SPARE 0x4404
|
|
#define CORE_DIG_CLANE_0_RW_CFG_0 0x5000
|
|
#define CORE_DIG_CLANE_0_RW_CFG_2 0x5002
|
|
#define CORE_DIG_CLANE_0_RW_LP_0 0x5040
|
|
#define CORE_DIG_CLANE_0_RW_LP_1 0x5041
|
|
#define CORE_DIG_CLANE_0_R_LP_0 0x5050
|
|
#define CORE_DIG_CLANE_0_R_LP_1 0x5051
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_0 0x5080
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_1 0x5081
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_2 0x5082
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_3 0x5083
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_4 0x5084
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_5 0x5085
|
|
#define CORE_DIG_CLANE_0_RW_HS_RX_6 0x5086
|
|
#define CORE_DIG_CLANE_0_R_RX_0 0x5090
|
|
#define CORE_DIG_CLANE_0_R_RX_1 0x5091
|
|
#define CORE_DIG_CLANE_0_R_TX_0 0x5092
|
|
#define CORE_DIG_CLANE_0_R_RX_2 0x5093
|
|
#define CORE_DIG_CLANE_0_R_RX_3 0x5094
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_0 0x5100
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_1 0x5101
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_2 0x5102
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_3 0x5103
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_4 0x5104
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_5 0x5105
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_6 0x5106
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_7 0x5107
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_8 0x5108
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_9 0x5109
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_10 0x510a
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_11 0x510b
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_12 0x510c
|
|
#define CORE_DIG_CLANE_0_RW_HS_TX_13 0x510d
|
|
#define CORE_DIG_CLANE_1_RW_CFG_0 0x5200
|
|
#define CORE_DIG_CLANE_1_RW_CFG_2 0x5202
|
|
#define CORE_DIG_CLANE_1_RW_LP_0 0x5240
|
|
#define CORE_DIG_CLANE_1_RW_LP_1 0x5241
|
|
#define CORE_DIG_CLANE_1_R_LP_0 0x5250
|
|
#define CORE_DIG_CLANE_1_R_LP_1 0x5251
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_0 0x5280
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_1 0x5281
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_2 0x5282
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_3 0x5283
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_4 0x5284
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_5 0x5285
|
|
#define CORE_DIG_CLANE_1_RW_HS_RX_6 0x5286
|
|
#define CORE_DIG_CLANE_1_R_RX_0 0x5290
|
|
#define CORE_DIG_CLANE_1_R_RX_1 0x5291
|
|
#define CORE_DIG_CLANE_1_R_TX_0 0x5292
|
|
#define CORE_DIG_CLANE_1_R_RX_2 0x5293
|
|
#define CORE_DIG_CLANE_1_R_RX_3 0x5294
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_0 0x5300
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_1 0x5301
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_2 0x5302
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_3 0x5303
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_4 0x5304
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_5 0x5305
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_6 0x5306
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_7 0x5307
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_8 0x5308
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_9 0x5309
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_10 0x530a
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_11 0x530b
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_12 0x530c
|
|
#define CORE_DIG_CLANE_1_RW_HS_TX_13 0x530d
|
|
#define CORE_DIG_CLANE_2_RW_CFG_0 0x5400
|
|
#define CORE_DIG_CLANE_2_RW_CFG_2 0x5402
|
|
#define CORE_DIG_CLANE_2_RW_LP_0 0x5440
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#define CORE_DIG_CLANE_2_RW_LP_1 0x5441
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#define CORE_DIG_CLANE_2_R_LP_0 0x5450
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#define CORE_DIG_CLANE_2_R_LP_1 0x5451
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#define CORE_DIG_CLANE_2_RW_HS_RX_0 0x5480
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#define CORE_DIG_CLANE_2_RW_HS_RX_1 0x5481
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#define CORE_DIG_CLANE_2_RW_HS_RX_2 0x5482
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#define CORE_DIG_CLANE_2_RW_HS_RX_3 0x5483
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#define CORE_DIG_CLANE_2_RW_HS_RX_4 0x5484
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#define CORE_DIG_CLANE_2_RW_HS_RX_5 0x5485
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#define CORE_DIG_CLANE_2_RW_HS_RX_6 0x5486
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#define CORE_DIG_CLANE_2_R_RX_0 0x5490
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#define CORE_DIG_CLANE_2_R_RX_1 0x5491
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#define CORE_DIG_CLANE_2_R_TX_0 0x5492
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#define CORE_DIG_CLANE_2_R_RX_2 0x5493
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#define CORE_DIG_CLANE_2_R_RX_3 0x5494
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#define CORE_DIG_CLANE_2_RW_HS_TX_0 0x5500
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#define CORE_DIG_CLANE_2_RW_HS_TX_1 0x5501
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#define CORE_DIG_CLANE_2_RW_HS_TX_2 0x5502
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#define CORE_DIG_CLANE_2_RW_HS_TX_3 0x5503
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#define CORE_DIG_CLANE_2_RW_HS_TX_4 0x5504
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#define CORE_DIG_CLANE_2_RW_HS_TX_5 0x5505
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#define CORE_DIG_CLANE_2_RW_HS_TX_6 0x5506
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#define CORE_DIG_CLANE_2_RW_HS_TX_7 0x5507
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#define CORE_DIG_CLANE_2_RW_HS_TX_8 0x5508
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#define CORE_DIG_CLANE_2_RW_HS_TX_9 0x5509
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#define CORE_DIG_CLANE_2_RW_HS_TX_10 0x550a
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#define CORE_DIG_CLANE_2_RW_HS_TX_11 0x550b
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#define CORE_DIG_CLANE_2_RW_HS_TX_12 0x550c
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#define CORE_DIG_CLANE_2_RW_HS_TX_13 0x550d
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#define PPI_STARTUP_RW_COMMON_DPHY_0_PWR_DWN_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_0_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_1_BG_ON_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_1_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_2_RCAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_2_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_3_PLL_START_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_3_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_4_HS_DCO_CAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_4_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_5_OFFSET_CAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_5_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_6_LP_DCO_CAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_6_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_7_DPHY_DDL_CAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_7_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_8_CPHY_DDL_CAL_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_8_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_9_DESKEW_1P1_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_9_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_A_HIBERNATE_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_A_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_DPHY_10_PHY_READY_addr_MASK 0xff
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#define PPI_STARTUP_RW_COMMON_DPHY_10_RESERVED_15_8_MASK 0x0
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#define PPI_STARTUP_RW_COMMON_STARTUP_1_1_PHY_READY_DLY_MASK 0xfff
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#define PPI_STARTUP_RW_COMMON_STARTUP_1_1_RESERVED_15_12_MASK 0x0
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0_LANE_CALIB_OFFSETCAL_LAST_MASK 0x1f
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0_LANE_CALIB_OFFSETCAL_EN_MASK 0x3e0
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0_OFFSETCAL_RECALIBRATION_EN_MASK 0x400
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0_TERMCAL_RECALIBRATION_EN_MASK 0x800
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0_RESERVED_15_12_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_1_DDL_COUNTER_TARGET_OBS_LSBs_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_2_DDL_COUNTER_TARGET_OBS_MSBs_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_2_DDL_COUNTER_MULT_OBS_LSBs_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_3_DDL_COUNTER_MULT_OBS_MSBs_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_3_RESERVED_15_8_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_4_DDL_COUNTER_SUM_OBS_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_4_RESERVED_15_11_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5_DDL_CAL_STATUS0_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5_DDL_CAL_STATUS1_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5_DDL_CAL_STATUS2_MASK 0x0
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#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5_DDL_CAL_STATUS3_MASK 0x0
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#define PPI_CALIBCTRL_RW_COMMON_BG_0_BG_MAX_COUNTER_MASK 0x1ff
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#define PPI_CALIBCTRL_RW_COMMON_BG_0_RESERVED_15_9_MASK 0x0
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_7_STATE_DONE_TIMER_THRES_MASK 0x1f
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#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_7_RESERVED_15_5_MASK 0x0
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#define PPI_CALIBCTRL_RW_ADC_CFG_0_ADC_ENB_MASK 0x1
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#define PPI_CALIBCTRL_RW_ADC_CFG_0_RESERVED_15_1_MASK 0x0
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#define PPI_CALIBCTRL_RW_ADC_CFG_1_ADC_WAIT_THRESH_T1_MASK 0xff
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#define PPI_CALIBCTRL_RW_ADC_CFG_1_ADC_WAIT_THRESH_T2_MASK 0xff00
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#define PPI_CALIBCTRL_R_ADC_DEBUG_CB_ATB_SEL_DAC_MASK 0x0
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#define PPI_CALIBCTRL_R_ADC_DEBUG_ADC_DONE_MASK 0x0
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#define PPI_CALIBCTRL_R_ADC_DEBUG_RESERVED_15_11_MASK 0x0
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCO_CLKEN_MASK 0x1
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCO_CLKEN_EN_MASK 0x2
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCOEN_MASK 0x4
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCOEN_EN_MASK 0x8
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCO_PON_MASK 0x10
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_LPDCO_PON_EN_MASK 0x20
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_FWORD_LATCH_MASK 0x40
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_FWORD_MASK 0x3f80
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_CAL_EN_MASK 0x4000
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#define PPI_RW_LPDCOCAL_TOP_OVERRIDE_LPCDCOCAL_I_MAN_TRIGGER_MASK 0x8000
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#define PPI_RW_LPDCOCAL_TIMEBASE_LPCDCOCAL_TIMEBASE_MASK 0x3ff
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#define PPI_RW_LPDCOCAL_TIMEBASE_RESERVED_15_10_MASK 0x0
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#define PPI_RW_LPDCOCAL_NREF_LPDCOCAL_NREF_MASK 0x7ff
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#define PPI_RW_LPDCOCAL_NREF_RESERVED_15_11_MASK 0x0
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#define PPI_RW_LPDCOCAL_NREF_RANGE_LPDCOCAL_NREF_RANGE_MASK 0x1f
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#define PPI_RW_LPDCOCAL_NREF_RANGE_RESERVED_15_5_MASK 0x0
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#define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN_LPDCOCAL_CMU_REF_TRIGGER_OVR_VAL_MASK 0x1
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#define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN_LPDCOCAL_CMU_REF_TRIGGER_OVR_EN_MASK 0x2
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#define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN_RESERVED_15_2_MASK 0x0
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#define PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_COARSE_MASK 0x1ff
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#define PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_PON_MASK 0xfe00
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#define PPI_RW_LPDCOCAL_VT_CONFIG_LPCDCOCAL_VT_TRACKING_EN_MASK 0x1
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#define PPI_RW_LPDCOCAL_VT_CONFIG_LPCDCOCAL_USE_IDEAL_NREF_MASK 0x2
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#define PPI_RW_LPDCOCAL_VT_CONFIG_LPCDCOCAL_VT_NREF_RANGE_MASK 0x7c
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#define PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_TWAIT_FINE_MASK 0xff80
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#define PPI_R_LPDCOCAL_DEBUG_RB_LPDCOCAL_N_MEAS_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_RB_LPDCOCAL_ERROR_RB_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_RB_LPDCOCAL_CAL_DONE_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_RB_LPDCOCAL_N_MEAS_DONE_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_RB_LPDCOCAL_ERROR_VT_RB_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_RB_RESERVED_15_15_MASK 0x0
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#define PPI_RW_LPDCOCAL_COARSE_CFG_NCOARSE_START_MASK 0x3
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#define PPI_RW_LPDCOCAL_COARSE_CFG_NCOARSE_DIAG_MASK 0xc
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#define PPI_RW_LPDCOCAL_COARSE_CFG_SCALE_REF_MASK 0x1f0
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#define PPI_RW_LPDCOCAL_COARSE_CFG_RESERVED_15_9_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_RB_LPDCOCAL_CAL_BOUND_STATUS_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_RB_LPDCOCAL_CAL_COARSE_HIT_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_RB_LPDCOCAL_PON_STATE_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_RB_RESERVED_15_10_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_0_RB_LPDCOCAL_STORED_MEAS_0_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_0_RB_RESERVED_15_11_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_1_RB_LPDCOCAL_STORED_MEAS_1_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_1_RB_RESERVED_15_11_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_FWORD_RB_LPDCOCAL_STORED_FWORD_0_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_COARSE_FWORD_RB_LPDCOCAL_STORED_FWORD_1_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_CURR_ERROR_LPDCOCAL_MEAS_CURR_ERROR_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_CURR_ERROR_RESERVED_15_12_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_LAST_ERROR_LPDCOCAL_LAST_MEAS_ERROR_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_LAST_ERROR_LPDCOCAL_VT_STATE_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_MEASURE_LAST_ERROR_RESERVED_15_15_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_VT_LPDCOCAL_N_WITHIN_RANGE_VT_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_VT_LPDCOCAL_N_BELOW_RANGE_VT_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_VT_LPDCOCAL_N_ABOVE_RANGE_VT_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_VT_LPDCOCAL_MEAS_ADJ_P0_VT_MASK 0x0
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#define PPI_R_LPDCOCAL_DEBUG_VT_RESERVED_15_14_MASK 0x0
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#define PPI_RW_LB_TIMEBASE_CONFIG_LOOPBACK_TIMEBASE_MASK 0xffff
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#define PPI_RW_LB_STARTCMU_CONFIG_LB_START_CMU_MASK 0x1
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#define PPI_RW_LB_STARTCMU_CONFIG_RESERVED_15_1_MASK 0x0
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#define PPI_R_LBPULSE_COUNTER_RB_LB_PULSE_COUNTER_MASK 0x0
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#define PPI_R_LB_START_CMU_RB_LB_STOP_CMU_MASK 0x0
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#define PPI_R_LB_START_CMU_RB_RESERVED_15_1_MASK 0x0
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#define PPI_RW_LB_DPHY_BURST_START_LBERT_DPHY_TXREQUESTHS_CLK_MASK 0x1
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#define PPI_RW_LB_DPHY_BURST_START_LBERT_DPHY_TXREQUESTHS_DATA_MASK 0x2
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#define PPI_RW_LB_DPHY_BURST_START_LBERT_DPHY_TXDATATRANSFERENHS_DATA_MASK 0x4
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#define PPI_RW_LB_DPHY_BURST_START_LBERT_DPHY_TXSKEWCALHS_DATA_MASK 0x8
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#define PPI_RW_LB_DPHY_BURST_START_LBERT_DPHY_TXALTERNATECALHS_DATA_MASK 0x10
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#define PPI_RW_LB_DPHY_BURST_START_RESERVED_15_5_MASK 0x0
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#define PPI_RW_LB_CPHY_BURST_START_LBERT_CPHY_TXREQUESTHS_DATA_MASK 0x1
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#define PPI_RW_LB_CPHY_BURST_START_LBERT_CPHY_TXDATATRANSFERENHS_DATA_MASK 0x2
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#define PPI_RW_LB_CPHY_BURST_START_RESERVED_15_2_MASK 0x0
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#define PPI_RW_DDLCAL_CFG_0_DDLCAL_TIMEBASE_TARGET_MASK 0x3ff
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#define PPI_RW_DDLCAL_CFG_0_RESERVED_15_10_MASK 0x0
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#define PPI_RW_DDLCAL_CFG_1_DDLCAL_MAX_PHASE_MASK 0xff
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#define PPI_RW_DDLCAL_CFG_1_DDLCAL_DISABLE_TIME_MASK 0xff00
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#define PPI_RW_DDLCAL_CFG_2_DDLCAL_ENABLE_WAIT_MASK 0xff
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#define PPI_RW_DDLCAL_CFG_2_DDLCAL_DDL_DLL_MASK 0x100
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#define PPI_RW_DDLCAL_CFG_2_DDLCAL_UPDATE_SETTINGS_MASK 0x200
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#define PPI_RW_DDLCAL_CFG_2_DDLCAL_TUNE_MODE_MASK 0xc00
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#define PPI_RW_DDLCAL_CFG_2_DDLCAL_WAIT_MASK 0xf000
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#define PPI_RW_DDLCAL_CFG_3_DDLCAL_COUNTER_REF_MASK 0x3ff
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#define PPI_RW_DDLCAL_CFG_3_RESERVED_15_10_MASK 0x0
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#define PPI_RW_DDLCAL_CFG_4_DDLCAL_STUCK_THRESH_MASK 0x3ff
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#define PPI_RW_DDLCAL_CFG_4_RESERVED_15_10_MASK 0x0
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#define PPI_RW_DDLCAL_CFG_5_DDLCAL_DDL_COARSE_BANK_MASK 0xf
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#define PPI_RW_DDLCAL_CFG_5_DDLCAL_DLL_FBK_MASK 0x3f0
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#define PPI_RW_DDLCAL_CFG_5_RESERVED_15_10_MASK 0x0
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#define PPI_RW_DDLCAL_CFG_6_DDLCAL_MAX_DIFF_MASK 0x3ff
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#define PPI_RW_DDLCAL_CFG_6_DDLCAL_CLEAR_COUNT_THRESH_MASK 0xfc00
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#define PPI_RW_DDLCAL_CFG_7_DDLCAL_START_DELAY_MASK 0x7f
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#define PPI_RW_DDLCAL_CFG_7_DDLCAL_DECR_WAIT_MASK 0x1f80
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#define PPI_RW_DDLCAL_CFG_7_RESERVED_15_13_MASK 0x0
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#define PPI_R_DDLCAL_DEBUG_0_DDLCAL_COUNTER0_MASK 0x0
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#define PPI_R_DDLCAL_DEBUG_0_RESERVED_15_10_MASK 0x0
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#define PPI_R_DDLCAL_DEBUG_1_DDLCAL_COUNTERX_MASK 0x0
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#define PPI_R_DDLCAL_DEBUG_1_RESERVED_15_10_MASK 0x0
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#define PPI_RW_PARITY_TEST_CR_PARITY_TESTCLEAR_MASK 0x1
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#define PPI_RW_PARITY_TEST_CR_PARITY_TESTSET_MASK 0x2
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#define PPI_RW_PARITY_TEST_RESERVED_15_2_MASK 0x0
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#define PPI_RW_STARTUP_OVR_0_STARTUP_STATE_OVR_VAL_MASK 0x1f
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#define PPI_RW_STARTUP_OVR_0_RESERVED_15_5_MASK 0x0
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#define PPI_RW_STARTUP_STATE_OVR_1_STARTUP_STATE_OVR_EN_MASK 0x1
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#define PPI_RW_STARTUP_STATE_OVR_1_TXCLKESC_BYPASS_MASK 0x2
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#define PPI_RW_STARTUP_STATE_OVR_1_RESERVED_15_2_MASK 0x0
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#define PPI_RW_DTB_SELECTOR_DTB_SELECT_ADDR_MASK 0xff
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#define PPI_RW_DTB_SELECTOR_DTB_SOURCE_SELECT_MASK 0x100
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#define PPI_RW_DTB_SELECTOR_RESERVED_15_9_MASK 0x0
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#define PPI_RW_DPHY_CLK_SPARE_DPHY_CLK_LANE_SPARE_MASK 0xffff
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#define PPI_RW_COMMON_CFG_CFG_CLK_DIV_FACTOR_MASK 0x3
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#define PPI_RW_COMMON_CFG_RESERVED_15_2_MASK 0x0
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#define PPI_RW_TERMCAL_CFG_0_TERMCAL_TIMER_MASK 0x7f
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#define PPI_RW_TERMCAL_CFG_0_RESERVED_15_7_MASK 0x0
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#define PPI_R_TERMCAL_DEBUG_0_TERMCAL_COMP_UNCHANGED_MASK 0x0
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#define PPI_R_TERMCAL_DEBUG_0_TERMCAL_CAL_ERROR_MASK 0x0
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#define PPI_R_TERMCAL_DEBUG_0_RESERVED_15_2_MASK 0x0
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#define PPI_RW_OFFSETCAL_CFG_0_OFFSETCAL_WAIT_THRESH_MASK 0x1f
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#define PPI_RW_OFFSETCAL_CFG_0_OFFSETCAL_CALIB_MODE_MASK 0x20
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#define PPI_RW_OFFSETCAL_CFG_0_RESERVED_15_6_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE0_OFFSETCAL_ERRCAL_RIGHT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE0_OFFSETCAL_ERRCAL_LEFT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE0_RESERVED_15_8_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE1_OFFSETCAL_ERRCAL_RIGHT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE1_OFFSETCAL_ERRCAL_LEFT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE1_RESERVED_15_8_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE2_OFFSETCAL_ERRCAL_RIGHT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE2_OFFSETCAL_ERRCAL_LEFT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE2_RESERVED_15_8_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE3_OFFSETCAL_ERRCAL_RIGHT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE3_OFFSETCAL_ERRCAL_LEFT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE3_RESERVED_15_8_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE4_OFFSETCAL_ERRCAL_RIGHT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE4_OFFSETCAL_ERRCAL_LEFT_MASK 0x0
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#define PPI_R_OFFSETCAL_DEBUG_LANE4_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXACTIVEHS_D0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXSYNCHS_D0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXVALIDHS_D0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXSKEWCALHS_D0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXWORDCLKHS_D0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXDATAHS_D0_OVR_VAL_MASK 0x1fe0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_O_RXALTERNATECALHS_D0_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXACTIVEHS_D0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXSYNCHS_D0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXVALIDHS_D0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXSKEWCALHS_D0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXWORDCLKHS_D0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXDATAHS_D0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_I_TXREQUESTHS_D0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_I_TXDATATRANSFERENHS_D0_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_TXREADYHS_D0_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_TXWORDCLKHS_D0_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_I_TXDATAHS_D0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_O_RXALTERNATECALHS_D0_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_I_TXREQUESTHS_D0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_I_TXDATATRANSFERENHS_D0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_O_TXREADYHS_D0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_O_TXWORDCLKHS_D0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_I_TXDATAHS_D0_OVR_VAL_MASK 0xff0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_I_TXSKEWCALHS_D0_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXREQUESTESC_D0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXLPDTESC_D0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXULPSEXIT_D0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXULPSESC_D0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXVALIDESC_D0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_O_TXREADYESC_D0_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXTRIGGERESC_D0_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXDATAESC_D0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXALTERNATECALHS_D0_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_I_TXSKEWCALHS_D0_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXREQUESTESC_D0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXLPDTESC_D0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXULPSEXIT_D0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXULPSESC_D0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXVALIDESC_D0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_O_TXREADYESC_D0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXTRIGGERESC_D0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXDATAESC_D0_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4_I_TXALTERNATECALHS_D0_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXCLKESC_D0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXLPDTESC_D0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXULPSESC_D0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXVALIDESC_D0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXTRIGGERESC_D0_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5_O_RXDATAESC_D0_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXCLKESC_D0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXLPDTESC_D0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXULPSESC_D0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXVALIDESC_D0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXTRIGGERESC_D0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_O_RXDATAESC_D0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_I_ENABLE_D0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_STOPSTATE_D0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ULPSACTIVENOT_D0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_I_TURNREQUEST_D0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_I_TURNDISABLE_D0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_DIRECTION_D0_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_I_FORCERXMODE_D0_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_I_FORCETXSTOPMODE_D0_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRESC_D0_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRSYNCESC_D0_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRCONTROL_D0_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRCONTENTIONLP0_D0_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRCONTENTIONLP1_D0_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRSOTHS_D0_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_O_ERRSOTSYNCHS_D0_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_I_ENABLE_D0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_STOPSTATE_D0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ULPSACTIVENOT_D0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_I_TURNREQUEST_D0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_I_TURNDISABLE_D0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_DIRECTION_D0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_I_FORCERXMODE_D0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_I_FORCETXSTOPMODE_D0_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRESC_D0_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRSYNCESC_D0_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRCONTROL_D0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRCONTENTIONLP0_D0_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRCONTENTIONLP1_D0_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRSOTHS_D0_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_O_ERRSOTSYNCHS_D0_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXACTIVEHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXSYNCHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXVALIDHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXSKEWCALHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXWORDCLKHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXDATAHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_O_RXALTERNATECALHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_I_TXREQUESTHS_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_I_TXDATATRANSFERENHS_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_O_TXREADYHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_O_TXWORDCLKHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_I_TXDATAHS_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_I_TXALTERNATECALHS_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_I_TXSKEWCALHS_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXREQUESTESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXLPDTESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXULPSEXIT_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXULPSESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXVALIDESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_O_TXREADYESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_I_TXTRIGGERESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_12_I_TXDATAESC_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_12_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXCLKESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXLPDTESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXULPSESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXVALIDESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXTRIGGERESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13_O_RXDATAESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_I_ENABLE_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_STOPSTATE_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ULPSACTIVENOT_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_I_TURNREQUEST_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_I_TURNDISABLE_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_DIRECTION_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_I_FORCERXMODE_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_I_FORCETXSTOPMODE_D0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRSYNCESC_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRCONTROL_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRCONTENTIONLP0_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRCONTENTIONLP1_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRSOTHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_O_ERRSOTSYNCHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXACTIVEHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXSYNCHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXVALIDHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXSKEWCALHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXWORDCLKHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_O_RXDATAHS_D0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_0_O_RXDATAHS_C0_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXACTIVEHS_C0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXSYNCHS_C0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXVALIDHS_C0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXINVALIDCODEHS_C0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXWORDCLKHS_C0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXSYNCTYPEHS_C0_OVR_VAL_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXALPVALIDHS_C0_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXALPCODE_C0_OVR_VAL_MASK 0x1e00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_O_RXALPNIBBLE_C0_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXACTIVEHS_C0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXSYNCHS_C0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXVALIDHS_C0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXINVALIDCODEHS_C0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXWORDCLKHS_C0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXSYNCTYPEHS_C0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXDATAHS_C0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXALPVALIDHS_C0_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXALPNIBBLE_C0_OVR_VAL_MASK 0xf00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_O_RXALPCODE_C0_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2_I_TXSYNCTYPEHS_C0_OVR_VAL_MASK 0xe000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_3_I_TXDATAHS_C0_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXREQUESTESC_C0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXLPDTESC_C0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXULPSEXIT_C0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXULPSESC_C0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXVALIDESC_C0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_O_TXREADYESC_C0_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXTRIGGERESC_C0_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXDATAESC_C0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXREQUESTHS_C0_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_I_TXDATATRANSFERENHS_C0_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_O_TXREADYHS_C0_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_O_TXWORDCLKHS_C0_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXREQUESTESC_C0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXLPDTESC_C0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXULPSEXIT_C0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXULPSESC_C0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXVALIDESC_C0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_O_TXREADYESC_C0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXTRIGGERESC_C0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_I_TXDATAESC_C0_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXCLKESC_C0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXLPDTESC_C0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXULPSESC_C0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXVALIDESC_C0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXTRIGGERESC_C0_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6_O_RXDATAESC_C0_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXCLKESC_C0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXLPDTESC_C0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXULPSESC_C0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXVALIDESC_C0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXTRIGGERESC_C0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_RXDATAESC_C0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_I_TXREQUESTHS_C0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_I_TXDATATRANSFERENHS_C0_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_TXREADYHS_C0_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_O_TXWORDCLKHS_C0_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_I_TXDATAHS_C0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_I_TXSENDSYNCHS_C0_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_I_TXSYNCTYPEHS_C0_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_ENABLE_C0_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_STOPSTATE_C0_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ULPSACTIVENOT_C0_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_TURNREQUEST_C0_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_TURNDISABLE_C0_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_DIRECTION_C0_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_FORCERXMODE_C0_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_FORCETXSTOPMODE_C0_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRESC_C0_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRSYNCESC_C0_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRCONTROL_C0_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRCONTENTIONLP0_C0_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRCONTENTIONLP1_C0_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_O_ERRSOTHS_C0_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_I_TXSENDSYNCHS_C0_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_I_ENABLE_C0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_STOPSTATE_C0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ULPSACTIVENOT_C0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_I_TURNREQUEST_C0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_I_TURNDISABLE_C0_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_DIRECTION_C0_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_I_FORCERXMODE_C0_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_I_FORCETXSTOPMODE_C0_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRESC_C0_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRSYNCESC_C0_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRCONTROL_C0_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRCONTENTIONLP0_C0_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRCONTENTIONLP1_C0_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_O_ERRSOTHS_C0_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_10_O_RXDATAHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXACTIVEHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXSYNCHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXVALIDHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXINVALIDCODEHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXWORDCLKHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXSYNCTYPEHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_O_RXALPCODE_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_I_TXSYNCTYPEHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12_O_RXALPVALIDHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12_O_RXALPNIBBLE_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12_I_TXDATAESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12_I_TXSENDSYNCHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_13_I_TXDATAHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXREQUESTESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXLPDTESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXULPSEXIT_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXULPSESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXVALIDESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_O_TXREADYESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXTRIGGERESC_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXREQUESTHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_I_TXDATATRANSFERENHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_O_TXREADYHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_O_TXWORDCLKHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXCLKESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXLPDTESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXULPSESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXVALIDESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXTRIGGERESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15_O_RXDATAESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_0_OA_LANE0_SPARE_IN_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_1_OA_LANE0_SPARE_IN_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_1_OA_LANE0_HSTX_LOWCAP_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_1_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_LANE0_SEL_LANE_CFG_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_L0_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_LANE0_HSRX_TERM_EN200OHMS_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_LANE0_HSRX_DPHY_DDL_PON_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_LANE0_HSTX_LOWCAP_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_OA_LANE0_HSTX_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSTX_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSTX_BOOST_EN_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSTX_SEL_PHASE0_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSTX_EQA_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSTX_SEL_CLKLB_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_LPTX_DIN_DN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_LPTX_DIN_DP_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSRX_DPHY_DDL_DCC_EN_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_OA_LANE0_HSRX_DPHY_DDL_EN_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_L0_CTRL_2_3_OA_L0_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSTX_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSTX_BOOST_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSTX_EQB_MASK 0x1c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSTX_CLK_OBS_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_LPTX_DIN_DN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_LPTX_DIN_DP_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_LPTX_SR_BYPASS_EN_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSTX_TERM_EN_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_OA_LANE0_HSRX_DPHY_DDL_DCC_EN_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_OA_LANE0_HSTX_DATA_AB_DPHY_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_OA_LANE0_HSTX_DATA_BC_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_OA_LANE0_HSTX_DATA_CA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_OA_LANE0_HSTX_TERM_EN_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_OA_LANE0_HSRX_DPHY_DDL_EN_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6_OA_LANE0_HSTX_DATA_BC_OVR_VAL_MASK 0x7f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6_OA_LANE0_HSTX_DATA_CA_OVR_VAL_MASK 0x3f80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6_OA_LANE0_HSTX_DATA_AB_DPHY_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6_OA_LANE0_HSRX_DPHY_DDL_PON_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPTX_EN_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPTX_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPTX_PULLDWN_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPRX_LP_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPRX_CD_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_LPRX_ULP_PON_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_HSRX_CPHY_CDR_FBK_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_HSRX_CPHY_CDR_FBK_CAP_PROG_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_OA_LANE0_HSRX_VCM_DET_SYNC_BYPASS_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPRX_LP_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPRX_CD_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPRX_ULP_PON_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPTX_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPTX_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_LPTX_PULLDWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CPHY_CDR_FBK_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CPHY_MASK_CHANGE_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CPHY_DELAY_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CDPHY_SEL_FAST_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_EQUALIZER_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_GMODE_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_HS_CLK_DIV_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_SEL_GATED_POLARITY_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_CPHY_CDR_DIV_MASK 0xe00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_CPHY_DELAY_OVR_VAL_MASK 0xf000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_TERM_RIGHT_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_TERM_LEFT_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_DPHY_CLK_CHANNEL_PULL_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_HS_CLK_DIV_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_DESERIALIZER_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_DESERIALIZER_DATA_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_DESERIALIZER_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_OFFCAL_OBS_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_VCM_DET_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_VCM_DET_OUT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_L0_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_L0_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_CPHY_MASK_CHANGE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSRX_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10_OA_LANE0_HSTX_DIV_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_TERM_RIGHT_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_TERM_LEFT_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_HS_CLK_DIV_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_DESERIALIZER_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_DESERIALIZER_DATA_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_DESERIALIZER_DIV_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_OFFCAL_OBS_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_VCM_DET_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_VCM_DET_OUT_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_L0_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_PON_OVR_VAL_MASK 0x1800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_OA_LANE0_HSRX_EN_OVR_VAL_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_L0_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_L0_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DDL_VT_COMP_BIAS_MASK 0x1e0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DATA_DELAY_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DDL_DIV_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_CPHY_FINE_RANGE_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_CPHY_SR_BYPASS_Z_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_VT_COMP_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DATA_DELAY_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_BIAS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_COARSE_BANK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_TUNE_MODE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DLL_FBK_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14_OA_LANE0_HSRX_DPHY_DDL_BIAS_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14_OA_LANE0_HSRX_DPHY_DDL_COARSE_BANK_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14_OA_LANE0_HSRX_DPHY_DDL_TUNE_MODE_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14_OA_LANE0_HSRX_DPHY_DLL_FBK_OVR_VAL_MASK 0xfc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_DPHY_DLL_CP_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_DPHY_CLK_CHANNEL_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_OFFCAL_RIGHT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_OFFCAL_LEFT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_DPHY_DDL_PHASE_MID_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_DPHY_DDL_PHASE_LEFT_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_HSRX_MODE_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15_OA_LANE0_ATB_SW_MASK 0xf800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_0_OA_LANE0_HSRX_OFFCAL_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_0_OA_LANE0_HSRX_OFFCAL_LEFT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_1_OA_LANE0_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_1_OA_LANE0_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2_OA_LANE0_HSRX_DPHY_DDL_PHASE_LEFT_OVR_VAL_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2_OA_LANE0_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2_OA_LANE0_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2_OA_LANE0_HSRX_MODE_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_3_IA_LANE0_HSRX_DATA_AB_LEFT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_3_IA_LANE0_HSRX_DATA_BC_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_DATA_CA_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_WORD_CLK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_HS_CLK_DIV_OUT_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSTX_WORD_CLK_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_VCM_DET_OUT_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_OUT_CAL_LEFT_N_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_OUT_CAL_LEFT_P_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_OUT_CAL_RIGHT_N_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4_IA_LANE0_HSRX_OUT_CAL_RIGHT_P_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_DATA_AB_LEFT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_DATA_BC_MID_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_DATA_CA_RIGHT_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_WORD_CLK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_HS_CLK_DIV_OUT_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSTX_WORD_CLK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_VCM_DET_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_OUT_CAL_LEFT_N_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_OUT_CAL_LEFT_P_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_OUT_CAL_RIGHT_N_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_OUT_CAL_RIGHT_P_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_DPHY_DDL_OSC_CLK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_L0_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_IA_LANE0_HSRX_CPHY_CDR_OSC_CLK_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_HSRX_DPHY_DDL_OSC_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_HSRX_CPHY_CDR_OSC_CLK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_LPRX_DOUTCD_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_LPRX_DOUTLP_OVR_VAL_MASK 0xc0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_LPRX_DOUTULP_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_IA_LANE0_SPARE_OUT_OVR_VAL_MASK 0x3c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7_IA_LANE0_LPRX_DOUTCD_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7_IA_LANE0_LPRX_DOUTLP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7_IA_LANE0_LPRX_DOUTULP_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7_IA_LANE0_SPARE_OUT_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSTX_BOOST_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSRX_DPHY_DDL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSTX_LOWCAP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_LPTX_DIN_DN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_LPTX_DIN_DP_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSRX_DPHY_DDL_DCC_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSRX_DPHY_DDL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8_OA_LANE0_HSRX_CPHY_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9_OA_LANE0_HSTX_DATA_AB_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9_OA_LANE0_HSTX_TERM_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9_OA_LANE0_HSTX_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_10_OA_LANE0_HSTX_DATA_BC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_10_OA_LANE0_HSTX_DATA_CA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPTX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPTX_PULLDWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPRX_LP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPRX_CD_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_LPRX_ULP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_HSRX_CPHY_CDR_FBK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_OA_LANE0_HSRX_CPHY_MASK_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_TERM_RIGHT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_TERM_LEFT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_HS_CLK_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_DESERIALIZER_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_DESERIALIZER_DATA_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_DESERIALIZER_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_OFFCAL_OBS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_VCM_DET_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_VCM_DET_OUT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_CPHY_ALP_DET_RIGHT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_CPHY_ALP_DET_LEFT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_OA_LANE0_HSRX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_DDL_BIAS_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_DDL_PHASE_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_DLL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_PREAMBLE_CAL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_OA_LANE0_HSRX_DPHY_DATA_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14_OA_LANE0_HSRX_DPHY_DDL_BIAS_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14_OA_LANE0_HSRX_DPHY_DDL_COARSE_BANK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14_OA_LANE0_HSRX_DPHY_DDL_TUNE_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14_OA_LANE0_HSRX_DPHY_DLL_FBK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_15_OA_LANE0_HSRX_OFFCAL_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_15_OA_LANE0_HSRX_OFFCAL_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_0_OA_LANE0_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_0_OA_LANE0_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1_OA_LANE0_HSRX_DPHY_DDL_PHASE_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1_OA_LANE0_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1_OA_LANE0_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1_OA_LANE0_HSRX_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_2_IA_LANE0_HSRX_DATA_AB_LEFT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_2_IA_LANE0_HSRX_DATA_BC_MID_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_DATA_CA_RIGHT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_HS_CLK_DIV_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSTX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_VCM_DET_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_OUT_CAL_LEFT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_OUT_CAL_LEFT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_OUT_CAL_RIGHT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3_IA_LANE0_HSRX_OUT_CAL_RIGHT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_HSRX_DPHY_DDL_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_HSRX_CPHY_ALP_DET_LEFT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_HSRX_CPHY_ALP_DET_RIGHT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_HSRX_CPHY_CDR_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_LPRX_DOUTCD_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_LPRX_DOUTLP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_LPRX_DOUTULP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_IA_LANE0_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_I_ENABLE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_STOPSTATE_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ULPSACTIVENOT_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_I_TURNREQUEST_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_I_TURNDISABLE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_DIRECTION_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_I_FORCERXMODE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_I_FORCETXSTOPMODE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRSYNCESC_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRCONTROL_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRCONTENTIONLP0_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRCONTENTIONLP1_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_O_ERRSOTHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_1_O_RXDATAHS_C0_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2_I_TXSENDALPHS_C0_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2_I_TXALPCODE_C0_OVR_VAL_MASK 0x3c
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2_I_TXALPNIBBLE_C0_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2_I_ALPWAKESTATE_C0_OVR_VAL_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3_I_TXSENDALPHS_C0_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3_I_TXALPCODE_C0_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3_I_TXALPNIBBLE_C0_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3_I_ALPWAKESTATE_C0_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4_I_TXSENDALPHS_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4_I_TXALPCODE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4_I_TXALPNIBBLE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4_I_ALPWAKESTATE_C0_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_RW_TRIO0_0_DESERIALIZER_DATA_EN_DELAY_THRESH_MASK 0x7
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#define CORE_DIG_RW_TRIO0_0_DESERIALIZER_DIV_EN_DELAY_THRESH_MASK 0x38
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#define CORE_DIG_RW_TRIO0_0_DESERIALIZER_DIV_EN_DELAY_DEASS_THRESH_MASK 0x1c0
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#define CORE_DIG_RW_TRIO0_0_POST_RECEIVED_RESET_THRESH_MASK 0xe00
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#define CORE_DIG_RW_TRIO0_0_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_RW_TRIO0_1_POST_DET_DELAY_THRESH_MASK 0xffff
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#define CORE_DIG_RW_TRIO0_2_DESERIALIZER_EN_DELAY_DEASS_THRESH_MASK 0xff
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#define CORE_DIG_RW_TRIO0_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXACTIVEHS_D1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXSYNCHS_D1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXVALIDHS_D1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXSKEWCALHS_D1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXWORDCLKHS_D1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXDATAHS_D1_OVR_VAL_MASK 0x1fe0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_O_RXALTERNATECALHS_D1_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXACTIVEHS_D1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXSYNCHS_D1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXVALIDHS_D1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXSKEWCALHS_D1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXWORDCLKHS_D1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXDATAHS_D1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_I_TXREQUESTHS_D1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_I_TXDATATRANSFERENHS_D1_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_TXREADYHS_D1_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_TXWORDCLKHS_D1_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_I_TXDATAHS_D1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_O_RXALTERNATECALHS_D1_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_I_TXREQUESTHS_D1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_I_TXDATATRANSFERENHS_D1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_O_TXREADYHS_D1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_O_TXWORDCLKHS_D1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_I_TXDATAHS_D1_OVR_VAL_MASK 0xff0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_I_TXSKEWCALHS_D1_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXREQUESTESC_D1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXLPDTESC_D1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXULPSEXIT_D1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXULPSESC_D1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXVALIDESC_D1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_O_TXREADYESC_D1_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXTRIGGERESC_D1_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXDATAESC_D1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXALTERNATECALHS_D1_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_I_TXSKEWCALHS_D1_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXREQUESTESC_D1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXLPDTESC_D1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXULPSEXIT_D1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXULPSESC_D1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXVALIDESC_D1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_O_TXREADYESC_D1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXTRIGGERESC_D1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXDATAESC_D1_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4_I_TXALTERNATECALHS_D1_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXCLKESC_D1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXLPDTESC_D1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXULPSESC_D1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXVALIDESC_D1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXTRIGGERESC_D1_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5_O_RXDATAESC_D1_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXCLKESC_D1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXLPDTESC_D1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXULPSESC_D1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXVALIDESC_D1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXTRIGGERESC_D1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_O_RXDATAESC_D1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_I_ENABLE_D1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_STOPSTATE_D1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ULPSACTIVENOT_D1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_I_TURNREQUEST_D1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_I_TURNDISABLE_D1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_DIRECTION_D1_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_I_FORCERXMODE_D1_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_I_FORCETXSTOPMODE_D1_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRESC_D1_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRSYNCESC_D1_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRCONTROL_D1_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRCONTENTIONLP0_D1_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRCONTENTIONLP1_D1_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRSOTHS_D1_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_O_ERRSOTSYNCHS_D1_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_I_ENABLE_D1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_STOPSTATE_D1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ULPSACTIVENOT_D1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_I_TURNREQUEST_D1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_I_TURNDISABLE_D1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_DIRECTION_D1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_I_FORCERXMODE_D1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_I_FORCETXSTOPMODE_D1_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRESC_D1_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRSYNCESC_D1_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRCONTROL_D1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRCONTENTIONLP0_D1_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRCONTENTIONLP1_D1_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRSOTHS_D1_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_O_ERRSOTSYNCHS_D1_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXACTIVEHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXSYNCHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXVALIDHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXSKEWCALHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXWORDCLKHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXDATAHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_O_RXALTERNATECALHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_I_TXREQUESTHS_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_I_TXDATATRANSFERENHS_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_O_TXREADYHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_O_TXWORDCLKHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_I_TXDATAHS_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_I_TXALTERNATECALHS_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_I_TXSKEWCALHS_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXREQUESTESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXLPDTESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXULPSEXIT_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXULPSESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXVALIDESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_O_TXREADYESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_I_TXTRIGGERESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_12_I_TXDATAESC_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_12_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXCLKESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXLPDTESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXULPSESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXVALIDESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXTRIGGERESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13_O_RXDATAESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_I_ENABLE_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_STOPSTATE_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ULPSACTIVENOT_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_I_TURNREQUEST_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_I_TURNDISABLE_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_DIRECTION_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_I_FORCERXMODE_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_I_FORCETXSTOPMODE_D1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRSYNCESC_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRCONTROL_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRCONTENTIONLP0_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRCONTENTIONLP1_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRSOTHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_O_ERRSOTSYNCHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXACTIVEHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXSYNCHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXVALIDHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXSKEWCALHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXWORDCLKHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_O_RXDATAHS_D1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_0_O_RXDATAHS_C1_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXACTIVEHS_C1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXSYNCHS_C1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXVALIDHS_C1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXINVALIDCODEHS_C1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXWORDCLKHS_C1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXSYNCTYPEHS_C1_OVR_VAL_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXALPVALIDHS_C1_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXALPCODE_C1_OVR_VAL_MASK 0x1e00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_O_RXALPNIBBLE_C1_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXACTIVEHS_C1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXSYNCHS_C1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXVALIDHS_C1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXINVALIDCODEHS_C1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXWORDCLKHS_C1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXSYNCTYPEHS_C1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXDATAHS_C1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXALPVALIDHS_C1_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXALPNIBBLE_C1_OVR_VAL_MASK 0xf00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_O_RXALPCODE_C1_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2_I_TXSYNCTYPEHS_C1_OVR_VAL_MASK 0xe000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_3_I_TXDATAHS_C1_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXREQUESTESC_C1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXLPDTESC_C1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXULPSEXIT_C1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXULPSESC_C1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXVALIDESC_C1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_O_TXREADYESC_C1_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXTRIGGERESC_C1_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXDATAESC_C1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXREQUESTHS_C1_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_I_TXDATATRANSFERENHS_C1_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_O_TXREADYHS_C1_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_O_TXWORDCLKHS_C1_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXREQUESTESC_C1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXLPDTESC_C1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXULPSEXIT_C1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXULPSESC_C1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXVALIDESC_C1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_O_TXREADYESC_C1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXTRIGGERESC_C1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_I_TXDATAESC_C1_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXCLKESC_C1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXLPDTESC_C1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXULPSESC_C1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXVALIDESC_C1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXTRIGGERESC_C1_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6_O_RXDATAESC_C1_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXCLKESC_C1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXLPDTESC_C1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXULPSESC_C1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXVALIDESC_C1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXTRIGGERESC_C1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_RXDATAESC_C1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_I_TXREQUESTHS_C1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_I_TXDATATRANSFERENHS_C1_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_TXREADYHS_C1_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_O_TXWORDCLKHS_C1_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_I_TXDATAHS_C1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_I_TXSENDSYNCHS_C1_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_I_TXSYNCTYPEHS_C1_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_ENABLE_C1_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_STOPSTATE_C1_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ULPSACTIVENOT_C1_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_TURNREQUEST_C1_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_TURNDISABLE_C1_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_DIRECTION_C1_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_FORCERXMODE_C1_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_FORCETXSTOPMODE_C1_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRESC_C1_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRSYNCESC_C1_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRCONTROL_C1_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRCONTENTIONLP0_C1_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRCONTENTIONLP1_C1_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_O_ERRSOTHS_C1_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_I_TXSENDSYNCHS_C1_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_I_ENABLE_C1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_STOPSTATE_C1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ULPSACTIVENOT_C1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_I_TURNREQUEST_C1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_I_TURNDISABLE_C1_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_DIRECTION_C1_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_I_FORCERXMODE_C1_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_I_FORCETXSTOPMODE_C1_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRESC_C1_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRSYNCESC_C1_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRCONTROL_C1_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRCONTENTIONLP0_C1_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRCONTENTIONLP1_C1_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_O_ERRSOTHS_C1_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_10_O_RXDATAHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXACTIVEHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXSYNCHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXVALIDHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXINVALIDCODEHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXWORDCLKHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXSYNCTYPEHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_O_RXALPCODE_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_I_TXSYNCTYPEHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12_O_RXALPVALIDHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12_O_RXALPNIBBLE_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12_I_TXDATAESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12_I_TXSENDSYNCHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_13_I_TXDATAHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXREQUESTESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXLPDTESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXULPSEXIT_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXULPSESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXVALIDESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_O_TXREADYESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXTRIGGERESC_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXREQUESTHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_I_TXDATATRANSFERENHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_O_TXREADYHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_O_TXWORDCLKHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXCLKESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXLPDTESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXULPSESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXVALIDESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXTRIGGERESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15_O_RXDATAESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_0_OA_LANE1_SPARE_IN_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_1_OA_LANE1_SPARE_IN_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_1_OA_LANE1_HSTX_LOWCAP_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_1_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_LANE1_SEL_LANE_CFG_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_L1_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_LANE1_HSRX_TERM_EN200OHMS_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_LANE1_HSRX_DPHY_DDL_PON_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_LANE1_HSTX_LOWCAP_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_OA_LANE1_HSTX_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSTX_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSTX_BOOST_EN_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSTX_SEL_PHASE0_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSTX_EQA_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSTX_SEL_CLKLB_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_LPTX_DIN_DN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_LPTX_DIN_DP_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSRX_DPHY_DDL_DCC_EN_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_OA_LANE1_HSRX_DPHY_DDL_EN_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_L1_CTRL_2_3_OA_L1_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSTX_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSTX_BOOST_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSTX_EQB_MASK 0x1c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSTX_CLK_OBS_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_LPTX_DIN_DN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_LPTX_DIN_DP_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_LPTX_SR_BYPASS_EN_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSTX_TERM_EN_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_OA_LANE1_HSRX_DPHY_DDL_DCC_EN_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_OA_LANE1_HSTX_DATA_AB_DPHY_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_OA_LANE1_HSTX_DATA_BC_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_OA_LANE1_HSTX_DATA_CA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_OA_LANE1_HSTX_TERM_EN_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_OA_LANE1_HSRX_DPHY_DDL_EN_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6_OA_LANE1_HSTX_DATA_BC_OVR_VAL_MASK 0x7f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6_OA_LANE1_HSTX_DATA_CA_OVR_VAL_MASK 0x3f80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6_OA_LANE1_HSTX_DATA_AB_DPHY_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6_OA_LANE1_HSRX_DPHY_DDL_PON_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPTX_EN_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPTX_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPTX_PULLDWN_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPRX_LP_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPRX_CD_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_LPRX_ULP_PON_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_HSRX_CPHY_CDR_FBK_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_HSRX_CPHY_CDR_FBK_CAP_PROG_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_OA_LANE1_HSRX_VCM_DET_SYNC_BYPASS_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPRX_LP_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPRX_CD_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPRX_ULP_PON_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPTX_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPTX_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_LPTX_PULLDWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CPHY_CDR_FBK_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CPHY_MASK_CHANGE_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CPHY_DELAY_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CDPHY_SEL_FAST_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_EQUALIZER_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_GMODE_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_HS_CLK_DIV_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_SEL_GATED_POLARITY_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_CPHY_CDR_DIV_MASK 0xe00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_CPHY_DELAY_OVR_VAL_MASK 0xf000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_TERM_RIGHT_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_TERM_LEFT_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_DPHY_CLK_CHANNEL_PULL_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_HS_CLK_DIV_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_DESERIALIZER_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_DESERIALIZER_DATA_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_DESERIALIZER_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_OFFCAL_OBS_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_VCM_DET_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_VCM_DET_OUT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_L1_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_L1_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_CPHY_MASK_CHANGE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSRX_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10_OA_LANE1_HSTX_DIV_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_TERM_RIGHT_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_TERM_LEFT_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_HS_CLK_DIV_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_DESERIALIZER_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_DESERIALIZER_DATA_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_DESERIALIZER_DIV_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_OFFCAL_OBS_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_VCM_DET_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_VCM_DET_OUT_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_L1_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_PON_OVR_VAL_MASK 0x1800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_OA_LANE1_HSRX_EN_OVR_VAL_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_L1_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_L1_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DDL_VT_COMP_BIAS_MASK 0x1e0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DATA_DELAY_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DDL_DIV_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_CPHY_FINE_RANGE_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_CPHY_SR_BYPASS_Z_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_VT_COMP_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DATA_DELAY_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_BIAS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_COARSE_BANK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_TUNE_MODE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DLL_FBK_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14_OA_LANE1_HSRX_DPHY_DDL_BIAS_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14_OA_LANE1_HSRX_DPHY_DDL_COARSE_BANK_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14_OA_LANE1_HSRX_DPHY_DDL_TUNE_MODE_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14_OA_LANE1_HSRX_DPHY_DLL_FBK_OVR_VAL_MASK 0xfc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_DPHY_DLL_CP_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_DPHY_CLK_CHANNEL_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_OFFCAL_RIGHT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_OFFCAL_LEFT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_DPHY_DDL_PHASE_MID_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_DPHY_DDL_PHASE_LEFT_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_HSRX_MODE_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15_OA_LANE1_ATB_SW_MASK 0xf800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_0_OA_LANE1_HSRX_OFFCAL_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_0_OA_LANE1_HSRX_OFFCAL_LEFT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_1_OA_LANE1_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_1_OA_LANE1_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2_OA_LANE1_HSRX_DPHY_DDL_PHASE_LEFT_OVR_VAL_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2_OA_LANE1_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2_OA_LANE1_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2_OA_LANE1_HSRX_MODE_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_3_IA_LANE1_HSRX_DATA_AB_LEFT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_3_IA_LANE1_HSRX_DATA_BC_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_DATA_CA_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_WORD_CLK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_HS_CLK_DIV_OUT_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSTX_WORD_CLK_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_VCM_DET_OUT_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_OUT_CAL_LEFT_N_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_OUT_CAL_LEFT_P_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_OUT_CAL_RIGHT_N_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4_IA_LANE1_HSRX_OUT_CAL_RIGHT_P_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_DATA_AB_LEFT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_DATA_BC_MID_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_DATA_CA_RIGHT_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_WORD_CLK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_HS_CLK_DIV_OUT_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSTX_WORD_CLK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_VCM_DET_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_OUT_CAL_LEFT_N_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_OUT_CAL_LEFT_P_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_OUT_CAL_RIGHT_N_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_OUT_CAL_RIGHT_P_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_DPHY_DDL_OSC_CLK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_L1_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_IA_LANE1_HSRX_CPHY_CDR_OSC_CLK_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_HSRX_DPHY_DDL_OSC_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_HSRX_CPHY_CDR_OSC_CLK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_LPRX_DOUTCD_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_LPRX_DOUTLP_OVR_VAL_MASK 0xc0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_LPRX_DOUTULP_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_IA_LANE1_SPARE_OUT_OVR_VAL_MASK 0x3c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7_IA_LANE1_LPRX_DOUTCD_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7_IA_LANE1_LPRX_DOUTLP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7_IA_LANE1_LPRX_DOUTULP_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7_IA_LANE1_SPARE_OUT_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSTX_BOOST_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSRX_DPHY_DDL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSTX_LOWCAP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_LPTX_DIN_DN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_LPTX_DIN_DP_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSRX_DPHY_DDL_DCC_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSRX_DPHY_DDL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8_OA_LANE1_HSRX_CPHY_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9_OA_LANE1_HSTX_DATA_AB_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9_OA_LANE1_HSTX_TERM_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9_OA_LANE1_HSTX_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_10_OA_LANE1_HSTX_DATA_BC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_10_OA_LANE1_HSTX_DATA_CA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPTX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPTX_PULLDWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPRX_LP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPRX_CD_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_LPRX_ULP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_HSRX_CPHY_CDR_FBK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_OA_LANE1_HSRX_CPHY_MASK_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_TERM_RIGHT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_TERM_LEFT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_HS_CLK_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_DESERIALIZER_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_DESERIALIZER_DATA_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_DESERIALIZER_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_OFFCAL_OBS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_VCM_DET_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_VCM_DET_OUT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_CPHY_ALP_DET_RIGHT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_CPHY_ALP_DET_LEFT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_OA_LANE1_HSRX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_DDL_BIAS_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_DDL_PHASE_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_DLL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_PREAMBLE_CAL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_OA_LANE1_HSRX_DPHY_DATA_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14_OA_LANE1_HSRX_DPHY_DDL_BIAS_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14_OA_LANE1_HSRX_DPHY_DDL_COARSE_BANK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14_OA_LANE1_HSRX_DPHY_DDL_TUNE_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14_OA_LANE1_HSRX_DPHY_DLL_FBK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_15_OA_LANE1_HSRX_OFFCAL_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_15_OA_LANE1_HSRX_OFFCAL_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_0_OA_LANE1_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_0_OA_LANE1_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1_OA_LANE1_HSRX_DPHY_DDL_PHASE_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1_OA_LANE1_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1_OA_LANE1_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1_OA_LANE1_HSRX_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_2_IA_LANE1_HSRX_DATA_AB_LEFT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_2_IA_LANE1_HSRX_DATA_BC_MID_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_DATA_CA_RIGHT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_HS_CLK_DIV_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSTX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_VCM_DET_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_OUT_CAL_LEFT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_OUT_CAL_LEFT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_OUT_CAL_RIGHT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3_IA_LANE1_HSRX_OUT_CAL_RIGHT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_HSRX_DPHY_DDL_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_HSRX_CPHY_ALP_DET_LEFT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_HSRX_CPHY_ALP_DET_RIGHT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_HSRX_CPHY_CDR_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_LPRX_DOUTCD_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_LPRX_DOUTLP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_LPRX_DOUTULP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_IA_LANE1_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_I_ENABLE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_STOPSTATE_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ULPSACTIVENOT_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_I_TURNREQUEST_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_I_TURNDISABLE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_DIRECTION_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_I_FORCERXMODE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_I_FORCETXSTOPMODE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRSYNCESC_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRCONTROL_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRCONTENTIONLP0_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRCONTENTIONLP1_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_O_ERRSOTHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_1_O_RXDATAHS_C1_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2_I_TXSENDALPHS_C1_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2_I_TXALPCODE_C1_OVR_VAL_MASK 0x3c
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2_I_TXALPNIBBLE_C1_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2_I_ALPWAKESTATE_C1_OVR_VAL_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3_I_TXSENDALPHS_C1_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3_I_TXALPCODE_C1_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3_I_TXALPNIBBLE_C1_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3_I_ALPWAKESTATE_C1_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4_I_TXSENDALPHS_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4_I_TXALPCODE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4_I_TXALPNIBBLE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4_I_ALPWAKESTATE_C1_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_RW_TRIO1_0_DESERIALIZER_DATA_EN_DELAY_THRESH_MASK 0x7
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#define CORE_DIG_RW_TRIO1_0_DESERIALIZER_DIV_EN_DELAY_THRESH_MASK 0x38
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#define CORE_DIG_RW_TRIO1_0_DESERIALIZER_DIV_EN_DELAY_DEASS_THRESH_MASK 0x1c0
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#define CORE_DIG_RW_TRIO1_0_POST_RECEIVED_RESET_THRESH_MASK 0xe00
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#define CORE_DIG_RW_TRIO1_0_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_RW_TRIO1_1_POST_DET_DELAY_THRESH_MASK 0xffff
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#define CORE_DIG_RW_TRIO1_2_DESERIALIZER_EN_DELAY_DEASS_THRESH_MASK 0xff
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#define CORE_DIG_RW_TRIO1_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXACTIVEHS_D2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXSYNCHS_D2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXVALIDHS_D2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXSKEWCALHS_D2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXWORDCLKHS_D2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXDATAHS_D2_OVR_VAL_MASK 0x1fe0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_O_RXALTERNATECALHS_D2_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXACTIVEHS_D2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXSYNCHS_D2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXVALIDHS_D2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXSKEWCALHS_D2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXWORDCLKHS_D2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXDATAHS_D2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_I_TXREQUESTHS_D2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_I_TXDATATRANSFERENHS_D2_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_TXREADYHS_D2_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_TXWORDCLKHS_D2_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_I_TXDATAHS_D2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_O_RXALTERNATECALHS_D2_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_I_TXREQUESTHS_D2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_I_TXDATATRANSFERENHS_D2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_O_TXREADYHS_D2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_O_TXWORDCLKHS_D2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_I_TXDATAHS_D2_OVR_VAL_MASK 0xff0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_I_TXSKEWCALHS_D2_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXREQUESTESC_D2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXLPDTESC_D2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXULPSEXIT_D2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXULPSESC_D2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXVALIDESC_D2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_O_TXREADYESC_D2_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXTRIGGERESC_D2_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXDATAESC_D2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXALTERNATECALHS_D2_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_I_TXSKEWCALHS_D2_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXREQUESTESC_D2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXLPDTESC_D2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXULPSEXIT_D2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXULPSESC_D2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXVALIDESC_D2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_O_TXREADYESC_D2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXTRIGGERESC_D2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXDATAESC_D2_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4_I_TXALTERNATECALHS_D2_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXCLKESC_D2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXLPDTESC_D2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXULPSESC_D2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXVALIDESC_D2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXTRIGGERESC_D2_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5_O_RXDATAESC_D2_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXCLKESC_D2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXLPDTESC_D2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXULPSESC_D2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXVALIDESC_D2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXTRIGGERESC_D2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_O_RXDATAESC_D2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_I_ENABLE_D2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_STOPSTATE_D2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ULPSACTIVENOT_D2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_I_TURNREQUEST_D2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_I_TURNDISABLE_D2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_DIRECTION_D2_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_I_FORCERXMODE_D2_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_I_FORCETXSTOPMODE_D2_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRESC_D2_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRSYNCESC_D2_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRCONTROL_D2_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRCONTENTIONLP0_D2_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRCONTENTIONLP1_D2_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRSOTHS_D2_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_O_ERRSOTSYNCHS_D2_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_I_ENABLE_D2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_STOPSTATE_D2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ULPSACTIVENOT_D2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_I_TURNREQUEST_D2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_I_TURNDISABLE_D2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_DIRECTION_D2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_I_FORCERXMODE_D2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_I_FORCETXSTOPMODE_D2_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRESC_D2_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRSYNCESC_D2_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRCONTROL_D2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRCONTENTIONLP0_D2_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRCONTENTIONLP1_D2_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRSOTHS_D2_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_O_ERRSOTSYNCHS_D2_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXACTIVEHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXSYNCHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXVALIDHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXSKEWCALHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXWORDCLKHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXDATAHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_O_RXALTERNATECALHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_I_TXREQUESTHS_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_I_TXDATATRANSFERENHS_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_O_TXREADYHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_O_TXWORDCLKHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_I_TXDATAHS_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_I_TXALTERNATECALHS_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_I_TXSKEWCALHS_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXREQUESTESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXLPDTESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXULPSEXIT_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXULPSESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXVALIDESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_O_TXREADYESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_I_TXTRIGGERESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_12_I_TXDATAESC_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_12_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXCLKESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXLPDTESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXULPSESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXVALIDESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXTRIGGERESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13_O_RXDATAESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_I_ENABLE_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_STOPSTATE_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ULPSACTIVENOT_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_I_TURNREQUEST_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_I_TURNDISABLE_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_DIRECTION_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_I_FORCERXMODE_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_I_FORCETXSTOPMODE_D2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRSYNCESC_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRCONTROL_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRCONTENTIONLP0_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRCONTENTIONLP1_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRSOTHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_O_ERRSOTSYNCHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXACTIVEHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXSYNCHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXVALIDHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXSKEWCALHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXWORDCLKHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_O_RXDATAHS_D2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_0_O_RXDATAHS_C2_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXACTIVEHS_C2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXSYNCHS_C2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXVALIDHS_C2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXINVALIDCODEHS_C2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXWORDCLKHS_C2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXSYNCTYPEHS_C2_OVR_VAL_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXALPVALIDHS_C2_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXALPCODE_C2_OVR_VAL_MASK 0x1e00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_O_RXALPNIBBLE_C2_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXACTIVEHS_C2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXSYNCHS_C2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXVALIDHS_C2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXINVALIDCODEHS_C2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXWORDCLKHS_C2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXSYNCTYPEHS_C2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXDATAHS_C2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXALPVALIDHS_C2_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXALPNIBBLE_C2_OVR_VAL_MASK 0xf00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_O_RXALPCODE_C2_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2_I_TXSYNCTYPEHS_C2_OVR_VAL_MASK 0xe000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_3_I_TXDATAHS_C2_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXREQUESTESC_C2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXLPDTESC_C2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXULPSEXIT_C2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXULPSESC_C2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXVALIDESC_C2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_O_TXREADYESC_C2_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXTRIGGERESC_C2_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXDATAESC_C2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXREQUESTHS_C2_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_I_TXDATATRANSFERENHS_C2_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_O_TXREADYHS_C2_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_O_TXWORDCLKHS_C2_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXREQUESTESC_C2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXLPDTESC_C2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXULPSEXIT_C2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXULPSESC_C2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXVALIDESC_C2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_O_TXREADYESC_C2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXTRIGGERESC_C2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_I_TXDATAESC_C2_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXCLKESC_C2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXLPDTESC_C2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXULPSESC_C2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXVALIDESC_C2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXTRIGGERESC_C2_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6_O_RXDATAESC_C2_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXCLKESC_C2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXLPDTESC_C2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXULPSESC_C2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXVALIDESC_C2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXTRIGGERESC_C2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_RXDATAESC_C2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_I_TXREQUESTHS_C2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_I_TXDATATRANSFERENHS_C2_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_TXREADYHS_C2_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_O_TXWORDCLKHS_C2_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_I_TXDATAHS_C2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_I_TXSENDSYNCHS_C2_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_I_TXSYNCTYPEHS_C2_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_ENABLE_C2_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_STOPSTATE_C2_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ULPSACTIVENOT_C2_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_TURNREQUEST_C2_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_TURNDISABLE_C2_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_DIRECTION_C2_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_FORCERXMODE_C2_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_FORCETXSTOPMODE_C2_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRESC_C2_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRSYNCESC_C2_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRCONTROL_C2_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRCONTENTIONLP0_C2_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRCONTENTIONLP1_C2_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_O_ERRSOTHS_C2_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_I_TXSENDSYNCHS_C2_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_I_ENABLE_C2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_STOPSTATE_C2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ULPSACTIVENOT_C2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_I_TURNREQUEST_C2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_I_TURNDISABLE_C2_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_DIRECTION_C2_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_I_FORCERXMODE_C2_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_I_FORCETXSTOPMODE_C2_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRESC_C2_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRSYNCESC_C2_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRCONTROL_C2_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRCONTENTIONLP0_C2_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRCONTENTIONLP1_C2_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_O_ERRSOTHS_C2_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_10_O_RXDATAHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXACTIVEHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXSYNCHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXVALIDHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXINVALIDCODEHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXWORDCLKHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXSYNCTYPEHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_O_RXALPCODE_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_I_TXSYNCTYPEHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12_O_RXALPVALIDHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12_O_RXALPNIBBLE_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12_I_TXDATAESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12_I_TXSENDSYNCHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_13_I_TXDATAHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXREQUESTESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXLPDTESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXULPSEXIT_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXULPSESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXVALIDESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_O_TXREADYESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXTRIGGERESC_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXREQUESTHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_I_TXDATATRANSFERENHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_O_TXREADYHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_O_TXWORDCLKHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXCLKESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXLPDTESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXULPSESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXVALIDESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXTRIGGERESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15_O_RXDATAESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_0_OA_LANE2_SPARE_IN_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_1_OA_LANE2_SPARE_IN_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_1_OA_LANE2_HSTX_LOWCAP_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_1_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_LANE2_SEL_LANE_CFG_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_L2_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_LANE2_HSRX_TERM_EN200OHMS_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_LANE2_HSRX_DPHY_DDL_PON_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_LANE2_HSTX_LOWCAP_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_OA_LANE2_HSTX_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSTX_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSTX_BOOST_EN_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSTX_SEL_PHASE0_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSTX_EQA_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSTX_SEL_CLKLB_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_LPTX_DIN_DN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_LPTX_DIN_DP_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSRX_DPHY_DDL_DCC_EN_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_OA_LANE2_HSRX_DPHY_DDL_EN_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_L2_CTRL_2_3_OA_L2_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSTX_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSTX_BOOST_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSTX_EQB_MASK 0x1c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSTX_CLK_OBS_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_LPTX_DIN_DN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_LPTX_DIN_DP_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_LPTX_SR_BYPASS_EN_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSTX_TERM_EN_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_OA_LANE2_HSRX_DPHY_DDL_DCC_EN_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_OA_LANE2_HSTX_DATA_AB_DPHY_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_OA_LANE2_HSTX_DATA_BC_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_OA_LANE2_HSTX_DATA_CA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_OA_LANE2_HSTX_TERM_EN_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_OA_LANE2_HSRX_DPHY_DDL_EN_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6_OA_LANE2_HSTX_DATA_BC_OVR_VAL_MASK 0x7f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6_OA_LANE2_HSTX_DATA_CA_OVR_VAL_MASK 0x3f80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6_OA_LANE2_HSTX_DATA_AB_DPHY_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6_OA_LANE2_HSRX_DPHY_DDL_PON_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPTX_EN_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPTX_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPTX_PULLDWN_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPRX_LP_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPRX_CD_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_LPRX_ULP_PON_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_HSRX_CPHY_CDR_FBK_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_HSRX_CPHY_CDR_FBK_CAP_PROG_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_OA_LANE2_HSRX_VCM_DET_SYNC_BYPASS_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPRX_LP_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPRX_CD_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPRX_ULP_PON_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPTX_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPTX_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_LPTX_PULLDWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CPHY_CDR_FBK_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CPHY_MASK_CHANGE_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CPHY_DELAY_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CDPHY_SEL_FAST_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_EQUALIZER_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_GMODE_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_HS_CLK_DIV_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_SEL_GATED_POLARITY_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_CPHY_CDR_DIV_MASK 0xe00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_CPHY_DELAY_OVR_VAL_MASK 0xf000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_TERM_RIGHT_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_TERM_LEFT_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_DPHY_CLK_CHANNEL_PULL_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_HS_CLK_DIV_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_DESERIALIZER_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_DESERIALIZER_DATA_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_DESERIALIZER_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_OFFCAL_OBS_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_VCM_DET_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_VCM_DET_OUT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_L2_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_L2_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_CPHY_MASK_CHANGE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSRX_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10_OA_LANE2_HSTX_DIV_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_TERM_RIGHT_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_TERM_LEFT_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_HS_CLK_DIV_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_DESERIALIZER_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_DESERIALIZER_DATA_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_DESERIALIZER_DIV_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_OFFCAL_OBS_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_VCM_DET_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_VCM_DET_OUT_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_L2_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_PON_OVR_VAL_MASK 0x1800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_OA_LANE2_HSRX_EN_OVR_VAL_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_L2_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_L2_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DDL_VT_COMP_BIAS_MASK 0x1e0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DATA_DELAY_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DDL_DIV_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_CPHY_FINE_RANGE_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_CPHY_SR_BYPASS_Z_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_VT_COMP_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DATA_DELAY_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_BIAS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_COARSE_BANK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_TUNE_MODE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DLL_FBK_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14_OA_LANE2_HSRX_DPHY_DDL_BIAS_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14_OA_LANE2_HSRX_DPHY_DDL_COARSE_BANK_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14_OA_LANE2_HSRX_DPHY_DDL_TUNE_MODE_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14_OA_LANE2_HSRX_DPHY_DLL_FBK_OVR_VAL_MASK 0xfc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_DPHY_DLL_CP_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_DPHY_CLK_CHANNEL_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_OFFCAL_RIGHT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_OFFCAL_LEFT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_DPHY_DDL_PHASE_MID_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_DPHY_DDL_PHASE_LEFT_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_HSRX_MODE_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15_OA_LANE2_ATB_SW_MASK 0xf800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_0_OA_LANE2_HSRX_OFFCAL_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_0_OA_LANE2_HSRX_OFFCAL_LEFT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_1_OA_LANE2_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_1_OA_LANE2_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2_OA_LANE2_HSRX_DPHY_DDL_PHASE_LEFT_OVR_VAL_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2_OA_LANE2_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2_OA_LANE2_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2_OA_LANE2_HSRX_MODE_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_3_IA_LANE2_HSRX_DATA_AB_LEFT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_3_IA_LANE2_HSRX_DATA_BC_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_DATA_CA_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_WORD_CLK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_HS_CLK_DIV_OUT_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSTX_WORD_CLK_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_VCM_DET_OUT_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_OUT_CAL_LEFT_N_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_OUT_CAL_LEFT_P_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_OUT_CAL_RIGHT_N_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4_IA_LANE2_HSRX_OUT_CAL_RIGHT_P_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_DATA_AB_LEFT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_DATA_BC_MID_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_DATA_CA_RIGHT_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_WORD_CLK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_HS_CLK_DIV_OUT_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSTX_WORD_CLK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_VCM_DET_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_OUT_CAL_LEFT_N_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_OUT_CAL_LEFT_P_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_OUT_CAL_RIGHT_N_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_OUT_CAL_RIGHT_P_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_DPHY_DDL_OSC_CLK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_L2_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_IA_LANE2_HSRX_CPHY_CDR_OSC_CLK_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_HSRX_DPHY_DDL_OSC_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_HSRX_CPHY_CDR_OSC_CLK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_LPRX_DOUTCD_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_LPRX_DOUTLP_OVR_VAL_MASK 0xc0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_LPRX_DOUTULP_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_IA_LANE2_SPARE_OUT_OVR_VAL_MASK 0x3c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7_IA_LANE2_LPRX_DOUTCD_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7_IA_LANE2_LPRX_DOUTLP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7_IA_LANE2_LPRX_DOUTULP_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7_IA_LANE2_SPARE_OUT_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSTX_BOOST_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSRX_DPHY_DDL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSTX_LOWCAP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_LPTX_DIN_DN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_LPTX_DIN_DP_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSRX_DPHY_DDL_DCC_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSRX_DPHY_DDL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8_OA_LANE2_HSRX_CPHY_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9_OA_LANE2_HSTX_DATA_AB_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9_OA_LANE2_HSTX_TERM_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9_OA_LANE2_HSTX_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_10_OA_LANE2_HSTX_DATA_BC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_10_OA_LANE2_HSTX_DATA_CA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPTX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPTX_PULLDWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPRX_LP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPRX_CD_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_LPRX_ULP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_HSRX_CPHY_CDR_FBK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_OA_LANE2_HSRX_CPHY_MASK_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_TERM_RIGHT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_TERM_LEFT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_HS_CLK_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_DESERIALIZER_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_DESERIALIZER_DATA_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_DESERIALIZER_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_OFFCAL_OBS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_VCM_DET_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_VCM_DET_OUT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_CPHY_ALP_DET_RIGHT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_CPHY_ALP_DET_LEFT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_OA_LANE2_HSRX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_DDL_BIAS_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_DDL_PHASE_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_DLL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_PREAMBLE_CAL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_OA_LANE2_HSRX_DPHY_DATA_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14_OA_LANE2_HSRX_DPHY_DDL_BIAS_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14_OA_LANE2_HSRX_DPHY_DDL_COARSE_BANK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14_OA_LANE2_HSRX_DPHY_DDL_TUNE_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14_OA_LANE2_HSRX_DPHY_DLL_FBK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_15_OA_LANE2_HSRX_OFFCAL_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_15_OA_LANE2_HSRX_OFFCAL_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_0_OA_LANE2_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_0_OA_LANE2_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1_OA_LANE2_HSRX_DPHY_DDL_PHASE_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1_OA_LANE2_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1_OA_LANE2_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1_OA_LANE2_HSRX_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_2_IA_LANE2_HSRX_DATA_AB_LEFT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_2_IA_LANE2_HSRX_DATA_BC_MID_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_DATA_CA_RIGHT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_HS_CLK_DIV_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSTX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_VCM_DET_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_OUT_CAL_LEFT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_OUT_CAL_LEFT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_OUT_CAL_RIGHT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3_IA_LANE2_HSRX_OUT_CAL_RIGHT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_HSRX_DPHY_DDL_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_HSRX_CPHY_ALP_DET_LEFT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_HSRX_CPHY_ALP_DET_RIGHT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_HSRX_CPHY_CDR_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_LPRX_DOUTCD_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_LPRX_DOUTLP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_LPRX_DOUTULP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_IA_LANE2_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_I_ENABLE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_STOPSTATE_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ULPSACTIVENOT_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_I_TURNREQUEST_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_I_TURNDISABLE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_DIRECTION_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_I_FORCERXMODE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_I_FORCETXSTOPMODE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRSYNCESC_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRCONTROL_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRCONTENTIONLP0_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRCONTENTIONLP1_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_O_ERRSOTHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_1_O_RXDATAHS_C2_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2_I_TXSENDALPHS_C2_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2_I_TXALPCODE_C2_OVR_VAL_MASK 0x3c
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2_I_TXALPNIBBLE_C2_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2_I_ALPWAKESTATE_C2_OVR_VAL_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3_I_TXSENDALPHS_C2_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3_I_TXALPCODE_C2_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3_I_TXALPNIBBLE_C2_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3_I_ALPWAKESTATE_C2_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4_I_TXSENDALPHS_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4_I_TXALPCODE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4_I_TXALPNIBBLE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4_I_ALPWAKESTATE_C2_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_RW_TRIO2_0_DESERIALIZER_DATA_EN_DELAY_THRESH_MASK 0x7
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#define CORE_DIG_RW_TRIO2_0_DESERIALIZER_DIV_EN_DELAY_THRESH_MASK 0x38
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#define CORE_DIG_RW_TRIO2_0_DESERIALIZER_DIV_EN_DELAY_DEASS_THRESH_MASK 0x1c0
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#define CORE_DIG_RW_TRIO2_0_POST_RECEIVED_RESET_THRESH_MASK 0xe00
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#define CORE_DIG_RW_TRIO2_0_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_RW_TRIO2_1_POST_DET_DELAY_THRESH_MASK 0xffff
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#define CORE_DIG_RW_TRIO2_2_DESERIALIZER_EN_DELAY_DEASS_THRESH_MASK 0xff
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#define CORE_DIG_RW_TRIO2_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXACTIVEHS_D3_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXSYNCHS_D3_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXVALIDHS_D3_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXSKEWCALHS_D3_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXWORDCLKHS_D3_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXDATAHS_D3_OVR_VAL_MASK 0x1fe0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_O_RXALTERNATECALHS_D3_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXACTIVEHS_D3_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXSYNCHS_D3_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXVALIDHS_D3_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXSKEWCALHS_D3_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXWORDCLKHS_D3_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXDATAHS_D3_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_I_TXREQUESTHS_D3_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_I_TXDATATRANSFERENHS_D3_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_TXREADYHS_D3_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_TXWORDCLKHS_D3_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_I_TXDATAHS_D3_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_O_RXALTERNATECALHS_D3_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_I_TXREQUESTHS_D3_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_I_TXDATATRANSFERENHS_D3_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_O_TXREADYHS_D3_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_O_TXWORDCLKHS_D3_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_I_TXDATAHS_D3_OVR_VAL_MASK 0xff0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_I_TXSKEWCALHS_D3_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXREQUESTESC_D3_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXLPDTESC_D3_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXULPSEXIT_D3_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXULPSESC_D3_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXVALIDESC_D3_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_O_TXREADYESC_D3_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXTRIGGERESC_D3_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXDATAESC_D3_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXALTERNATECALHS_D3_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_I_TXSKEWCALHS_D3_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXREQUESTESC_D3_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXLPDTESC_D3_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXULPSEXIT_D3_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXULPSESC_D3_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXVALIDESC_D3_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_O_TXREADYESC_D3_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXTRIGGERESC_D3_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXDATAESC_D3_OVR_VAL_MASK 0x7f80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4_I_TXALTERNATECALHS_D3_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXCLKESC_D3_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXLPDTESC_D3_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXULPSESC_D3_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXVALIDESC_D3_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXTRIGGERESC_D3_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5_O_RXDATAESC_D3_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXCLKESC_D3_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXLPDTESC_D3_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXULPSESC_D3_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXVALIDESC_D3_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXTRIGGERESC_D3_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_O_RXDATAESC_D3_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_I_ENABLE_D3_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_STOPSTATE_D3_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ULPSACTIVENOT_D3_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_I_TURNREQUEST_D3_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_I_TURNDISABLE_D3_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_DIRECTION_D3_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_I_FORCERXMODE_D3_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_I_FORCETXSTOPMODE_D3_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRESC_D3_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRSYNCESC_D3_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRCONTROL_D3_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRCONTENTIONLP0_D3_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRCONTENTIONLP1_D3_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRSOTHS_D3_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_O_ERRSOTSYNCHS_D3_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_I_ENABLE_D3_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_STOPSTATE_D3_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ULPSACTIVENOT_D3_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_I_TURNREQUEST_D3_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_I_TURNDISABLE_D3_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_DIRECTION_D3_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_I_FORCERXMODE_D3_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_I_FORCETXSTOPMODE_D3_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRESC_D3_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRSYNCESC_D3_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRCONTROL_D3_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRCONTENTIONLP0_D3_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRCONTENTIONLP1_D3_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRSOTHS_D3_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_O_ERRSOTSYNCHS_D3_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXACTIVEHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXSYNCHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXVALIDHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXSKEWCALHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXWORDCLKHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXDATAHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_O_RXALTERNATECALHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_I_TXREQUESTHS_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_I_TXDATATRANSFERENHS_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_O_TXREADYHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_O_TXWORDCLKHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_I_TXDATAHS_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_I_TXALTERNATECALHS_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_I_TXSKEWCALHS_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXREQUESTESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXLPDTESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXULPSEXIT_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXULPSESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXVALIDESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_O_TXREADYESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_I_TXTRIGGERESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_12_I_TXDATAESC_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_12_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXCLKESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXLPDTESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXULPSESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXVALIDESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXTRIGGERESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13_O_RXDATAESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_I_ENABLE_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_STOPSTATE_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ULPSACTIVENOT_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_I_TURNREQUEST_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_I_TURNDISABLE_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_DIRECTION_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_I_FORCERXMODE_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_I_FORCETXSTOPMODE_D3_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRSYNCESC_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRCONTROL_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRCONTENTIONLP0_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRCONTENTIONLP1_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRSOTHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_O_ERRSOTSYNCHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXACTIVEHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXSYNCHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXVALIDHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXSKEWCALHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXWORDCLKHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_O_RXDATAHS_D3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_0_OA_LANE3_SPARE_IN_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_1_OA_LANE3_SPARE_IN_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_1_OA_LANE3_HSTX_LOWCAP_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_1_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_LANE3_SEL_LANE_CFG_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_L3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_LANE3_HSRX_TERM_EN200OHMS_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_LANE3_HSRX_DPHY_DDL_PON_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_LANE3_HSTX_LOWCAP_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_OA_LANE3_HSTX_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSTX_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSTX_BOOST_EN_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSTX_SEL_PHASE0_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSTX_EQA_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSTX_SEL_CLKLB_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_LPTX_DIN_DN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_LPTX_DIN_DP_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSRX_DPHY_DDL_DCC_EN_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_OA_LANE3_HSRX_DPHY_DDL_EN_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_L3_CTRL_2_3_OA_L3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSTX_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSTX_BOOST_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSTX_EQB_MASK 0x1c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSTX_CLK_OBS_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_LPTX_DIN_DN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_LPTX_DIN_DP_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_LPTX_SR_BYPASS_EN_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSTX_TERM_EN_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_OA_LANE3_HSRX_DPHY_DDL_DCC_EN_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_OA_LANE3_HSTX_DATA_AB_DPHY_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_OA_LANE3_HSTX_DATA_BC_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_OA_LANE3_HSTX_DATA_CA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_OA_LANE3_HSTX_TERM_EN_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_OA_LANE3_HSRX_DPHY_DDL_EN_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6_OA_LANE3_HSTX_DATA_BC_OVR_VAL_MASK 0x7f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6_OA_LANE3_HSTX_DATA_CA_OVR_VAL_MASK 0x3f80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6_OA_LANE3_HSTX_DATA_AB_DPHY_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6_OA_LANE3_HSRX_DPHY_DDL_PON_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPTX_EN_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPTX_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPTX_PULLDWN_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPRX_LP_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPRX_CD_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_LPRX_ULP_PON_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_HSRX_CPHY_CDR_FBK_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_HSRX_CPHY_CDR_FBK_CAP_PROG_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_OA_LANE3_HSRX_VCM_DET_SYNC_BYPASS_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPRX_LP_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPRX_CD_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPRX_ULP_PON_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPTX_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPTX_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_LPTX_PULLDWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CPHY_CDR_FBK_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CPHY_MASK_CHANGE_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CPHY_DELAY_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CDPHY_SEL_FAST_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_EQUALIZER_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_GMODE_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_HS_CLK_DIV_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_SEL_GATED_POLARITY_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_CPHY_CDR_DIV_MASK 0xe00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_CPHY_DELAY_OVR_VAL_MASK 0xf000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_TERM_RIGHT_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_TERM_LEFT_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_DPHY_CLK_CHANNEL_PULL_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_HS_CLK_DIV_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_DESERIALIZER_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_DESERIALIZER_DATA_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_DESERIALIZER_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_OFFCAL_OBS_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_VCM_DET_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_VCM_DET_OUT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_L3_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_L3_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_CPHY_MASK_CHANGE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSRX_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10_OA_LANE3_HSTX_DIV_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_TERM_RIGHT_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_TERM_LEFT_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_HS_CLK_DIV_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_DESERIALIZER_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_DESERIALIZER_DATA_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_DESERIALIZER_DIV_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_OFFCAL_OBS_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_VCM_DET_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_VCM_DET_OUT_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_L3_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_PON_OVR_VAL_MASK 0x1800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_OA_LANE3_HSRX_EN_OVR_VAL_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_L3_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_L3_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DDL_VT_COMP_BIAS_MASK 0x1e0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DATA_DELAY_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DDL_DIV_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_CPHY_FINE_RANGE_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_CPHY_SR_BYPASS_Z_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_VT_COMP_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DATA_DELAY_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_BIAS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_COARSE_BANK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_TUNE_MODE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DLL_FBK_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14_OA_LANE3_HSRX_DPHY_DDL_BIAS_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14_OA_LANE3_HSRX_DPHY_DDL_COARSE_BANK_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14_OA_LANE3_HSRX_DPHY_DDL_TUNE_MODE_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14_OA_LANE3_HSRX_DPHY_DLL_FBK_OVR_VAL_MASK 0xfc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_DPHY_DLL_CP_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_DPHY_CLK_CHANNEL_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_OFFCAL_RIGHT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_OFFCAL_LEFT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_DPHY_DDL_PHASE_MID_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_DPHY_DDL_PHASE_LEFT_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_HSRX_MODE_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15_OA_LANE3_ATB_SW_MASK 0xf800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_0_OA_LANE3_HSRX_OFFCAL_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_0_OA_LANE3_HSRX_OFFCAL_LEFT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_1_OA_LANE3_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_1_OA_LANE3_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2_OA_LANE3_HSRX_DPHY_DDL_PHASE_LEFT_OVR_VAL_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2_OA_LANE3_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2_OA_LANE3_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2_OA_LANE3_HSRX_MODE_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_3_IA_LANE3_HSRX_DATA_AB_LEFT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_3_IA_LANE3_HSRX_DATA_BC_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_DATA_CA_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_WORD_CLK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_HS_CLK_DIV_OUT_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSTX_WORD_CLK_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_VCM_DET_OUT_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_OUT_CAL_LEFT_N_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_OUT_CAL_LEFT_P_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_OUT_CAL_RIGHT_N_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4_IA_LANE3_HSRX_OUT_CAL_RIGHT_P_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_DATA_AB_LEFT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_DATA_BC_MID_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_DATA_CA_RIGHT_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_WORD_CLK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_HS_CLK_DIV_OUT_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSTX_WORD_CLK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_VCM_DET_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_OUT_CAL_LEFT_N_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_OUT_CAL_LEFT_P_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_OUT_CAL_RIGHT_N_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_OUT_CAL_RIGHT_P_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_DPHY_DDL_OSC_CLK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_L3_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_IA_LANE3_HSRX_CPHY_CDR_OSC_CLK_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_HSRX_DPHY_DDL_OSC_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_HSRX_CPHY_CDR_OSC_CLK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_LPRX_DOUTCD_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_LPRX_DOUTLP_OVR_VAL_MASK 0xc0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_LPRX_DOUTULP_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_IA_LANE3_SPARE_OUT_OVR_VAL_MASK 0x3c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7_IA_LANE3_LPRX_DOUTCD_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7_IA_LANE3_LPRX_DOUTLP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7_IA_LANE3_LPRX_DOUTULP_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7_IA_LANE3_SPARE_OUT_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSTX_BOOST_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSRX_DPHY_DDL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSTX_LOWCAP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_LPTX_DIN_DN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_LPTX_DIN_DP_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSRX_DPHY_DDL_DCC_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSRX_DPHY_DDL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8_OA_LANE3_HSRX_CPHY_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9_OA_LANE3_HSTX_DATA_AB_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9_OA_LANE3_HSTX_TERM_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9_OA_LANE3_HSTX_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_10_OA_LANE3_HSTX_DATA_BC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_10_OA_LANE3_HSTX_DATA_CA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPTX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPTX_PULLDWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPRX_LP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPRX_CD_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_LPRX_ULP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_HSRX_CPHY_CDR_FBK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_OA_LANE3_HSRX_CPHY_MASK_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_TERM_RIGHT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_TERM_LEFT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_HS_CLK_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_DESERIALIZER_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_DESERIALIZER_DATA_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_DESERIALIZER_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_OFFCAL_OBS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_VCM_DET_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_VCM_DET_OUT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_CPHY_ALP_DET_RIGHT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_CPHY_ALP_DET_LEFT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_OA_LANE3_HSRX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_DDL_BIAS_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_DDL_PHASE_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_DLL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_PREAMBLE_CAL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_OA_LANE3_HSRX_DPHY_DATA_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14_OA_LANE3_HSRX_DPHY_DDL_BIAS_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14_OA_LANE3_HSRX_DPHY_DDL_COARSE_BANK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14_OA_LANE3_HSRX_DPHY_DDL_TUNE_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14_OA_LANE3_HSRX_DPHY_DLL_FBK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_15_OA_LANE3_HSRX_OFFCAL_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_15_OA_LANE3_HSRX_OFFCAL_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_0_OA_LANE3_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_0_OA_LANE3_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1_OA_LANE3_HSRX_DPHY_DDL_PHASE_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1_OA_LANE3_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1_OA_LANE3_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1_OA_LANE3_HSRX_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_2_IA_LANE3_HSRX_DATA_AB_LEFT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_2_IA_LANE3_HSRX_DATA_BC_MID_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_DATA_CA_RIGHT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_HS_CLK_DIV_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSTX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_VCM_DET_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_OUT_CAL_LEFT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_OUT_CAL_LEFT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_OUT_CAL_RIGHT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3_IA_LANE3_HSRX_OUT_CAL_RIGHT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_HSRX_DPHY_DDL_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_HSRX_CPHY_ALP_DET_LEFT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_HSRX_CPHY_ALP_DET_RIGHT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_HSRX_CPHY_CDR_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_LPRX_DOUTCD_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_LPRX_DOUTLP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_LPRX_DOUTULP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_IA_LANE3_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_0_OA_LANE4_SPARE_IN_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_1_OA_LANE4_SPARE_IN_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_1_OA_LANE4_HSTX_LOWCAP_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_1_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_LANE4_SEL_LANE_CFG_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_L4_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_LANE4_HSRX_TERM_EN200OHMS_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_LANE4_HSRX_DPHY_DDL_PON_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_LANE4_HSTX_LOWCAP_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_OA_LANE4_HSTX_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSTX_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSTX_BOOST_EN_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSTX_SEL_PHASE0_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSTX_EQA_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSTX_SEL_CLKLB_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_LPTX_DIN_DN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_LPTX_DIN_DP_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSRX_DPHY_DDL_DCC_EN_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_OA_LANE4_HSRX_DPHY_DDL_EN_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_L4_CTRL_2_3_OA_L4_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSTX_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSTX_BOOST_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSTX_EQB_MASK 0x1c
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSTX_CLK_OBS_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_LPTX_DIN_DN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_LPTX_DIN_DP_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_LPTX_SR_BYPASS_EN_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSTX_TERM_EN_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_OA_LANE4_HSRX_DPHY_DDL_DCC_EN_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_OA_LANE4_HSTX_DATA_AB_DPHY_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_OA_LANE4_HSTX_DATA_BC_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_OA_LANE4_HSTX_DATA_CA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_OA_LANE4_HSTX_TERM_EN_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_OA_LANE4_HSRX_DPHY_DDL_EN_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6_OA_LANE4_HSTX_DATA_BC_OVR_VAL_MASK 0x7f
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6_OA_LANE4_HSTX_DATA_CA_OVR_VAL_MASK 0x3f80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6_OA_LANE4_HSTX_DATA_AB_DPHY_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6_OA_LANE4_HSRX_DPHY_DDL_PON_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPTX_EN_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPTX_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPTX_PULLDWN_EN_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPRX_LP_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPRX_CD_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_LPRX_ULP_PON_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_HSRX_CPHY_CDR_FBK_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_HSRX_CPHY_CDR_FBK_CAP_PROG_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_OA_LANE4_HSRX_VCM_DET_SYNC_BYPASS_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPRX_LP_PON_OVR_VAL_MASK 0x3
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPRX_CD_PON_OVR_VAL_MASK 0xc
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPRX_ULP_PON_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPTX_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPTX_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_LPTX_PULLDWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CPHY_CDR_FBK_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CPHY_MASK_CHANGE_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CPHY_DELAY_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CDPHY_SEL_FAST_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_EQUALIZER_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_GMODE_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_HS_CLK_DIV_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_SEL_GATED_POLARITY_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_CPHY_CDR_DIV_MASK 0xe00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_CPHY_DELAY_OVR_VAL_MASK 0xf000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_TERM_RIGHT_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_TERM_LEFT_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_DPHY_CLK_CHANNEL_PULL_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_HS_CLK_DIV_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_DESERIALIZER_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_DESERIALIZER_DATA_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_DESERIALIZER_DIV_EN_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_OFFCAL_OBS_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_VCM_DET_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_VCM_DET_OUT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_L4_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_L4_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_CPHY_MASK_CHANGE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSRX_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10_OA_LANE4_HSTX_DIV_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_TERM_RIGHT_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_TERM_LEFT_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_HS_CLK_DIV_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_DESERIALIZER_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_DESERIALIZER_DATA_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_DESERIALIZER_DIV_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_OFFCAL_OBS_EN_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_VCM_DET_PON_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_VCM_DET_OUT_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_L4_HSRX_CPHY_ALP_DET_RIGHT_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_CPHY_ALP_DET_LEFT_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_PON_OVR_VAL_MASK 0x1800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_OA_LANE4_HSRX_EN_OVR_VAL_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_L4_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_L4_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DDL_VT_COMP_BIAS_MASK 0x1e0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DATA_DELAY_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DDL_DIV_MASK 0x1c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_CPHY_FINE_RANGE_MASK 0x6000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_CPHY_SR_BYPASS_Z_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_BIAS_BYPASS_EN_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_PHASE_CHANGE_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_PREAMBLE_CAL_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_VT_COMP_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DATA_DELAY_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_BIAS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_COARSE_BANK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_TUNE_MODE_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DLL_FBK_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14_OA_LANE4_HSRX_DPHY_DDL_BIAS_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14_OA_LANE4_HSRX_DPHY_DDL_COARSE_BANK_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14_OA_LANE4_HSRX_DPHY_DDL_TUNE_MODE_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14_OA_LANE4_HSRX_DPHY_DLL_FBK_OVR_VAL_MASK 0xfc00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_DPHY_DLL_CP_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_DPHY_CLK_CHANNEL_MASK 0x18
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_OFFCAL_RIGHT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_OFFCAL_LEFT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_DPHY_DDL_PHASE_MID_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_DPHY_DDL_PHASE_LEFT_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_HSRX_MODE_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15_OA_LANE4_ATB_SW_MASK 0xf800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_0_OA_LANE4_HSRX_OFFCAL_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_0_OA_LANE4_HSRX_OFFCAL_LEFT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_1_OA_LANE4_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_1_OA_LANE4_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2_OA_LANE4_HSRX_DPHY_DDL_PHASE_LEFT_OVR_VAL_MASK 0x1ff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2_OA_LANE4_HSRX_DPHY_DDL_PHASE_MID_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2_OA_LANE4_HSRX_DPHY_DDL_PHASE_RIGHT_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2_OA_LANE4_HSRX_MODE_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_3_IA_LANE4_HSRX_DATA_AB_LEFT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_3_IA_LANE4_HSRX_DATA_BC_MID_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_DATA_CA_RIGHT_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_WORD_CLK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_HS_CLK_DIV_OUT_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSTX_WORD_CLK_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_VCM_DET_OUT_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_OUT_CAL_LEFT_N_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_OUT_CAL_LEFT_P_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_OUT_CAL_RIGHT_N_OVR_VAL_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4_IA_LANE4_HSRX_OUT_CAL_RIGHT_P_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_DATA_AB_LEFT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_DATA_BC_MID_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_DATA_CA_RIGHT_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_WORD_CLK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_HS_CLK_DIV_OUT_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSTX_WORD_CLK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_VCM_DET_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_OUT_CAL_LEFT_N_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_OUT_CAL_LEFT_P_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_OUT_CAL_RIGHT_N_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_OUT_CAL_RIGHT_P_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_DPHY_DDL_OSC_CLK_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_L4_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_IA_LANE4_HSRX_CPHY_CDR_OSC_CLK_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_HSRX_DPHY_DDL_OSC_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_HSRX_CPHY_ALP_DET_LEFT_OUT_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_HSRX_CPHY_ALP_DET_RIGHT_OUT_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_HSRX_CPHY_CDR_OSC_CLK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_LPRX_DOUTCD_OVR_VAL_MASK 0x30
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_LPRX_DOUTLP_OVR_VAL_MASK 0xc0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_LPRX_DOUTULP_OVR_VAL_MASK 0x300
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_IA_LANE4_SPARE_OUT_OVR_VAL_MASK 0x3c00
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7_IA_LANE4_LPRX_DOUTCD_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7_IA_LANE4_LPRX_DOUTLP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7_IA_LANE4_LPRX_DOUTULP_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7_IA_LANE4_SPARE_OUT_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSTX_BOOST_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSRX_DPHY_DDL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSTX_LOWCAP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_LPTX_DIN_DN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_LPTX_DIN_DP_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSRX_DPHY_DDL_DCC_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSRX_DPHY_DDL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8_OA_LANE4_HSRX_CPHY_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9_OA_LANE4_HSTX_DATA_AB_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9_OA_LANE4_HSTX_TERM_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9_OA_LANE4_HSTX_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_10_OA_LANE4_HSTX_DATA_BC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_10_OA_LANE4_HSTX_DATA_CA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_10_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPTX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPTX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPTX_PULLDWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPRX_LP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPRX_CD_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_LPRX_ULP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_HSRX_CPHY_CDR_FBK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_OA_LANE4_HSRX_CPHY_MASK_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_TERM_RIGHT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_TERM_LEFT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_HS_CLK_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_DESERIALIZER_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_DESERIALIZER_DATA_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_DESERIALIZER_DIV_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_OFFCAL_OBS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_VCM_DET_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_VCM_DET_OUT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_CPHY_ALP_DET_RIGHT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_CPHY_ALP_DET_LEFT_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_OA_LANE4_HSRX_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_DDL_BIAS_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_DDL_PHASE_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_DLL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_PREAMBLE_CAL_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_OA_LANE4_HSRX_DPHY_DATA_DELAY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14_OA_LANE4_HSRX_DPHY_DDL_BIAS_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14_OA_LANE4_HSRX_DPHY_DDL_COARSE_BANK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14_OA_LANE4_HSRX_DPHY_DDL_TUNE_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14_OA_LANE4_HSRX_DPHY_DLL_FBK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_15_OA_LANE4_HSRX_OFFCAL_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_15_OA_LANE4_HSRX_OFFCAL_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_0_OA_LANE4_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_0_OA_LANE4_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1_OA_LANE4_HSRX_DPHY_DDL_PHASE_LEFT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1_OA_LANE4_HSRX_DPHY_DDL_PHASE_MID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1_OA_LANE4_HSRX_DPHY_DDL_PHASE_RIGHT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1_OA_LANE4_HSRX_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_2_IA_LANE4_HSRX_DATA_AB_LEFT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_2_IA_LANE4_HSRX_DATA_BC_MID_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_DATA_CA_RIGHT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_HS_CLK_DIV_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSTX_WORD_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_VCM_DET_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_OUT_CAL_LEFT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_OUT_CAL_LEFT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_OUT_CAL_RIGHT_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3_IA_LANE4_HSRX_OUT_CAL_RIGHT_P_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_HSRX_DPHY_DDL_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_HSRX_CPHY_ALP_DET_LEFT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_HSRX_CPHY_ALP_DET_RIGHT_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_HSRX_CPHY_CDR_OSC_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_LPRX_DOUTCD_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_LPRX_DOUTLP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_LPRX_DOUTULP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_IA_LANE4_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_ENABLE_DCK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_O_STOPSTATE_DCK_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_O_ULPSACTIVENOT_DCK_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_O_RXULPSCLKNOT_DCK_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_O_RXCLKACTIVEHS_DCK_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_TXREQUESTHS_DCK_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_FORCETXSTOPMODE_DCK_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_FORCERXMODE_DCK_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_TXULPSCLK_DCK_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_TXULPSEXIT_DCK_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_I_TXHSIDLECLKHS_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_O_TXHSIDLECLKREADYHS_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_ENABLE_DCK_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_O_STOPSTATE_DCK_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_O_ULPSACTIVENOT_DCK_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_O_RXULPSCLKNOT_DCK_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_O_RXCLKACTIVEHS_DCK_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_TXREQUESTHS_DCK_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_FORCETXSTOPMODE_DCK_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_FORCERXMODE_DCK_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_TXULPSCLK_DCK_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_TXULPSEXIT_DCK_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_I_TXHSIDLECLKHS_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_O_TXHSIDLECLKREADYHS_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_ENABLE_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_O_STOPSTATE_DCK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_O_ULPSACTIVENOT_DCK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_O_RXULPSCLKNOT_DCK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_O_RXCLKACTIVEHS_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_TXREQUESTHS_DCK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_FORCETXSTOPMODE_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_FORCERXMODE_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_TXULPSCLK_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_TXULPSEXIT_DCK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_I_TXHSIDLECLKHS_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_O_TXHSIDLECLKREADYHS_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_CFG_CLK_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_TXCLKESC_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_RST_N_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_PHY_MODE_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_CONT_EN_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_TEST_STOP_CLK_EN_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_O_OCLA_CLK_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_O_MON_OUT_VALID_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_PHY_STATE_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_PHY_CALIB_IN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_O_PHY_CALIB_OUT_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_I_RX_TX_N_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_CFG_CLK_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_TXCLKESC_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_RST_N_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_PHY_MODE_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_CONT_EN_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_TEST_STOP_CLK_EN_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_O_OCLA_CLK_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_O_MON_OUT_VALID_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_O_MON_OUT_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_O_CONT_DATA_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_O_DTB_OUT_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_I_RX_TX_N_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_2_I_PHY_STATE_OVR_VAL_MASK 0x1f
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_2_O_CONT_DATA_OVR_VAL_MASK 0xffe0
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_3_I_PHY_CALIB_IN_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_4_I_PHY_CALIB_IN_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_5_I_PHY_CALIB_IN_OVR_VAL_MASK 0xff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_5_O_DTB_OUT_OVR_VAL_MASK 0xff00
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_6_O_PHY_CALIB_OUT_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_7_O_MON_OUT_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_8_O_MON_OUT_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_9_O_MON_OUT_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_10_O_MON_OUT_OVR_VAL_MASK 0xffff
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_CFG_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_TXCLKESC_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_RST_N_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_PHY_MODE_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_CONT_EN_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_TEST_STOP_CLK_EN_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_O_OCLA_CLK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_O_MON_OUT_VALID_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_I_RX_TX_N_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_12_I_PHY_STATE_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_12_O_CONT_DATA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_13_I_PHY_CALIB_IN_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_14_I_PHY_CALIB_IN_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_15_I_PHY_CALIB_IN_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_15_O_DTB_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_0_O_PHY_CALIB_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_1_O_MON_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_2_O_MON_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_3_O_MON_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_4_O_MON_OUT_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_SEL_CPHY_DPHY_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_ATB_CLK_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_CHOP_CLK_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_CHOP_CLK_EN_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_PON_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_BG_PON_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_CAL_PON_OVR_VAL_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_CAL_UP_EN_OVR_VAL_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_CAL_DOWN_EN_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_ATB_COMP_PON_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_HSTX_VCOMM_REG_PON_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_IBIAS_PON_OVR_VAL_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_AMP1200_PON_OVR_VAL_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_VPCLK_REG_PON_OVR_VAL_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_ATB_SEL_DAC_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_SEL_CPHY_DPHY_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_ATB_CLK_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_CHOP_CLK_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_CHOP_CLK_EN_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_PON_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_BG_PON_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_CAL_PON_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_CAL_UP_EN_OVR_EN_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_CAL_DOWN_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_ATB_COMP_PON_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_HSTX_VCOMM_REG_PON_OVR_EN_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_IBIAS_PON_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_AMP1200_PON_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_VPCLK_REG_PON_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_ATB_SEL_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_ATB_SEL_DAC_OVR_VAL_MASK 0x3ff
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_ATB_SEL_OVR_VAL_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_ATB_EXT_CON_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_ATB_PROBE_BOOST_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_ATB_PROBE_VBE_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2_OA_CB_PLL_BUSTIEZ_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_SEL_LPTX_VREF_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_SEL_LPTX_PROG_MASK 0xe
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_SEL_MPLL_REG_VREF_MASK 0x70
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_SEL_HSTXLB_DCO_VREF_MASK 0x80
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_EN_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_EN_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_HSTXLB_DCO_SEL_DIV_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_HSTX_BOOST_PROG_MASK 0x7000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3_OA_CB_HSTX_VCOMM_REG_STBON_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_SEL_TRIO0_ALP_VREF_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_SEL_TRIO1_ALP_VREF_MASK 0x38
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_SEL_TRIO2_ALP_VREF_MASK 0x1c0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_SEL_HSRX_CM_DET_VREF_MASK 0x600
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_SEL_VCOMM_PROG_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_VCOMM_UNTERM_MODE_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4_OA_CB_CAL_SINK_EN_OVR_VAL_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_SPARE_IN_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_SETR_CALIB_VT_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_SEL_45OHM_50OHM_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_REXT_IOCONT_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_VPCLK_REG_MODE_MASK 0xc00
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_DSK_CLK_CHANNEL_MASK 0x3000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_SEL_EXT_INT_CHOP_CLK_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5_OA_CB_CAL_SINK_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_LP_DCO_PON_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_LP_DCO_EN_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_LP_DCO_CLK_EN_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_LP_DCO_FWORD_CHANGE_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_LP_DCO_FWORD_OVR_VAL_MASK 0x7f0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_HSTXLB_DCO_FWORD_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_HSTXLB_DCO_PON_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_HSTXLB_DCO_EN_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6_OA_CB_REXT_IOCONT_EN_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_LP_DCO_PON_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_LP_DCO_EN_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_LP_DCO_CLK_EN_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_LP_DCO_FWORD_CHANGE_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_LP_DCO_FWORD_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_HSTXLB_DCO_FWORD_OVR_VAL_MASK 0xe0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_HSTXLB_DCO_PON_OVR_VAL_MASK 0x100
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_HSTXLB_DCO_EN_OVR_VAL_MASK 0x200
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_VAL_MASK 0x400
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_SETR_OVR_EN_MASK 0x800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_SETR_CALIB_OVR_EN_MASK 0x1000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_SETRA_OVR_EN_MASK 0x2000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_SETRB_OVR_EN_MASK 0x4000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7_OA_CB_DSK_CLK_MODE_OVR_EN_MASK 0x8000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8_OA_SETR_OVR_VAL_MASK 0xf
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8_OA_SETR_CALIB_OVR_VAL_MASK 0xf0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8_OA_SETRA_OVR_VAL_MASK 0x700
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8_OA_SETRB_OVR_VAL_MASK 0x3800
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8_OA_CB_DSK_CLK_MODE_OVR_VAL_MASK 0xc000
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_ATB_COMP_OUT_OVR_VAL_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_DET_VP_OVR_VAL_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_DET_VPH_OVR_VAL_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_HSTXLB_CLKDIG_OVR_VAL_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_LP_DCO_CLK_OVR_VAL_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_REXT_IOCONT_OVR_VAL_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_IA_CB_SPARE_OUT_OVR_VAL_MASK 0x3c0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_ATB_COMP_OUT_OVR_EN_MASK 0x1
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_DET_VP_OVR_EN_MASK 0x2
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_DET_VPH_OVR_EN_MASK 0x4
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_HSTXLB_CLKDIG_OVR_EN_MASK 0x8
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_LP_DCO_CLK_OVR_EN_MASK 0x10
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_REXT_IOCONT_OVR_EN_MASK 0x20
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_IA_CB_SPARE_OUT_OVR_EN_MASK 0x40
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_11_OA_CB_VP2_PROG_MASK 0x7
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#define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_11_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_SEL_CPHY_DPHY_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_ATB_CLK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_CHOP_CLK_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_CHOP_CLK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_BG_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_CAL_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_CAL_UP_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_CAL_DOWN_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_ATB_COMP_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_HSTX_VCOMM_REG_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_IBIAS_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_AMP1200_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_VPCLK_REG_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_HSTXLB_DCO_CLK90_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12_OA_CB_REXT_IOCONT_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_OA_CB_ATB_SEL_DAC_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_OA_CB_ATB_SEL_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_OA_CB_CAL_SINK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_OA_CB_HSTXLB_DCO_CLK0_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_LP_DCO_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_LP_DCO_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_LP_DCO_CLK_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_LP_DCO_FWORD_CHANGE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_LP_DCO_FWORD_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_HSTXLB_DCO_FWORD_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_HSTXLB_DCO_PON_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14_OA_CB_HSTXLB_DCO_EN_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15_OA_SETR_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15_OA_SETR_CALIB_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15_OA_SETRA_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15_OA_SETRB_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15_OA_CB_DSK_CLK_MODE_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_ATB_COMP_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_DET_VP_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_DET_VPH_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_HSTXLB_CLKDIG_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_LP_DCO_CLK_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_REXT_IOCONT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_IA_CB_SPARE_OUT_INT_MASK 0x0
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#define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_0_DPHY_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_RW_COMMON_0_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_RW_COMMON_1_OCLA_DATA_SEL_MASK 0x1ff
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#define CORE_DIG_RW_COMMON_1_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_RW_COMMON_2_OCLA_DATA_SEL_MASK 0xff
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#define CORE_DIG_RW_COMMON_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_RW_COMMON_3_OCLA_CLK_SEL_MASK 0x1ff
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#define CORE_DIG_RW_COMMON_3_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_RW_COMMON_4_OCLA_CLK_SEL_MASK 0xff
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#define CORE_DIG_RW_COMMON_4_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_RW_COMMON_5_INPUT_SAMPLING_REG_MASK 0x1
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#define CORE_DIG_RW_COMMON_5_DTB_SELECT_MASK 0x1fe
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#define CORE_DIG_RW_COMMON_5_HSRX_DPHY_DLL_EN_DRV_MASK 0x200
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#define CORE_DIG_RW_COMMON_5_WORD_CLK_SEL_DLANE_MASK 0xc00
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#define CORE_DIG_RW_COMMON_5_WORD_CLK_SEL_CLANE_MASK 0x3000
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#define CORE_DIG_RW_COMMON_5_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_RW_COMMON_6_DESERIALIZER_DIV_EN_DELAY_THRESH_D_MASK 0x7
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#define CORE_DIG_RW_COMMON_6_DESERIALIZER_EN_DEASS_COUNT_THRESH_D_MASK 0x38
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#define CORE_DIG_RW_COMMON_6_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_RW_COMMON_7_LANE0_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x3
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#define CORE_DIG_RW_COMMON_7_LANE1_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0xc
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#define CORE_DIG_RW_COMMON_7_LANE2_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x30
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#define CORE_DIG_RW_COMMON_7_LANE3_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0xc0
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#define CORE_DIG_RW_COMMON_7_LANE4_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x300
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#define CORE_DIG_RW_COMMON_7_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_8_LANE0_HSRX_WORD_CLK_GATING_OVR_EN_MASK 0x1
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#define CORE_DIG_RW_COMMON_8_LANE0_HSRX_WORD_CLK_GATING_OVR_VAL_MASK 0x2
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#define CORE_DIG_RW_COMMON_8_LANE1_HSRX_WORD_CLK_GATING_OVR_EN_MASK 0x4
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#define CORE_DIG_RW_COMMON_8_LANE1_HSRX_WORD_CLK_GATING_OVR_VAL_MASK 0x8
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#define CORE_DIG_RW_COMMON_8_LANE2_HSRX_WORD_CLK_GATING_OVR_EN_MASK 0x10
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#define CORE_DIG_RW_COMMON_8_LANE2_HSRX_WORD_CLK_GATING_OVR_VAL_MASK 0x20
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#define CORE_DIG_RW_COMMON_8_LANE3_HSRX_WORD_CLK_GATING_OVR_EN_MASK 0x40
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#define CORE_DIG_RW_COMMON_8_LANE3_HSRX_WORD_CLK_GATING_OVR_VAL_MASK 0x80
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#define CORE_DIG_RW_COMMON_8_LANE4_HSRX_WORD_CLK_GATING_OVR_EN_MASK 0x100
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#define CORE_DIG_RW_COMMON_8_LANE4_HSRX_WORD_CLK_GATING_OVR_VAL_MASK 0x200
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#define CORE_DIG_RW_COMMON_8_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_9_LP_DCO_CLK_GATING_OVR_EN_MASK 0x1
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#define CORE_DIG_RW_COMMON_9_LP_DCO_CLK_GATING_OVR_VAL_MASK 0x2
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#define CORE_DIG_RW_COMMON_9_LP_DCO_CLK_SEL_GATING_REG_MASK 0xc
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#define CORE_DIG_RW_COMMON_9_HSTXLB_DCO_CLK_GATING_OVR_EN_MASK 0x10
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#define CORE_DIG_RW_COMMON_9_HSTXLB_DCO_CLK_GATING_OVR_VAL_MASK 0x20
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#define CORE_DIG_RW_COMMON_9_HSTXLB_DCO_CLK_SEL_GATING_REG_MASK 0xc0
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#define CORE_DIG_RW_COMMON_9_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_RW_COMMON_10_LANE0_CDROSC_CLK_SEL_GATING_REG_MASK 0x3
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#define CORE_DIG_RW_COMMON_10_LANE2_CDROSC_CLK_SEL_GATING_REG_MASK 0xc
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#define CORE_DIG_RW_COMMON_10_LANE3_CDROSC_CLK_SEL_GATING_REG_MASK 0x30
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#define CORE_DIG_RW_COMMON_10_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_RW_COMMON_11_LANE0_CDROSC_CLK_GATING_OVR_EN_MASK 0x1
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#define CORE_DIG_RW_COMMON_11_LANE0_CDROSC_CLK_GATING_OVR_VAL_MASK 0x2
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#define CORE_DIG_RW_COMMON_11_LANE2_CDROSC_CLK_GATING_OVR_EN_MASK 0x4
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#define CORE_DIG_RW_COMMON_11_LANE2_CDROSC_CLK_GATING_OVR_VAL_MASK 0x8
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#define CORE_DIG_RW_COMMON_11_LANE3_CDROSC_CLK_GATING_OVR_EN_MASK 0x10
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#define CORE_DIG_RW_COMMON_11_LANE3_CDROSC_CLK_GATING_OVR_VAL_MASK 0x20
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#define CORE_DIG_RW_COMMON_11_RESERVED_15_6_MASK 0x0
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#define CORE_DIG_RW_COMMON_12_LANE0_DDL_OSC_SEL_GATING_REG_MASK 0x3
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#define CORE_DIG_RW_COMMON_12_LANE1_DDL_OSC_SEL_GATING_REG_MASK 0xc
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#define CORE_DIG_RW_COMMON_12_LANE2_DDL_OSC_SEL_GATING_REG_MASK 0x30
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#define CORE_DIG_RW_COMMON_12_LANE3_DDL_OSC_SEL_GATING_REG_MASK 0xc0
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#define CORE_DIG_RW_COMMON_12_LANE4_DDL_OSC_SEL_GATING_REG_MASK 0x300
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#define CORE_DIG_RW_COMMON_12_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_13_LANE0_DDL_OSC_GATING_OVR_EN_MASK 0x1
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#define CORE_DIG_RW_COMMON_13_LANE0_DDL_OSC_GATING_OVR_VAL_MASK 0x2
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#define CORE_DIG_RW_COMMON_13_LANE1_DDL_OSC_GATING_OVR_EN_MASK 0x4
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#define CORE_DIG_RW_COMMON_13_LANE1_DDL_OSC_GATING_OVR_VAL_MASK 0x8
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#define CORE_DIG_RW_COMMON_13_LANE2_DDL_OSC_GATING_OVR_EN_MASK 0x10
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#define CORE_DIG_RW_COMMON_13_LANE2_DDL_OSC_GATING_OVR_VAL_MASK 0x20
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#define CORE_DIG_RW_COMMON_13_LANE3_DDL_OSC_GATING_OVR_EN_MASK 0x40
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#define CORE_DIG_RW_COMMON_13_LANE3_DDL_OSC_GATING_OVR_VAL_MASK 0x80
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#define CORE_DIG_RW_COMMON_13_LANE4_DDL_OSC_GATING_OVR_EN_MASK 0x100
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#define CORE_DIG_RW_COMMON_13_LANE4_DDL_OSC_GATING_OVR_VAL_MASK 0x200
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#define CORE_DIG_RW_COMMON_13_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_14_LANE0_HSTX_WORD_CLK_SEL_GATING_REG_MASK 0x3
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#define CORE_DIG_RW_COMMON_14_LANE1_HSTX_WORD_CLK_SEL_GATING_REG_MASK 0xc
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#define CORE_DIG_RW_COMMON_14_LANE2_HSTX_WORD_CLK_SEL_GATING_REG_MASK 0x30
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#define CORE_DIG_RW_COMMON_14_LANE3_HSTX_WORD_CLK_SEL_GATING_REG_MASK 0xc0
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#define CORE_DIG_RW_COMMON_14_LANE4_HSTX_WORD_CLK_SEL_GATING_REG_MASK 0x300
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#define CORE_DIG_RW_COMMON_14_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_RW_COMMON_15_LANE0_HSTX_WORD_CLK_GATING_OVR_EN_MASK 0x1
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#define CORE_DIG_RW_COMMON_15_LANE0_HSTX_WORD_CLK_GATING_OVR_VAL_MASK 0x2
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#define CORE_DIG_RW_COMMON_15_LANE1_HSTX_WORD_CLK_GATING_OVR_EN_MASK 0x4
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#define CORE_DIG_RW_COMMON_15_LANE1_HSTX_WORD_CLK_GATING_OVR_VAL_MASK 0x8
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#define CORE_DIG_RW_COMMON_15_LANE2_HSTX_WORD_CLK_GATING_OVR_EN_MASK 0x10
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#define CORE_DIG_RW_COMMON_15_LANE2_HSTX_WORD_CLK_GATING_OVR_VAL_MASK 0x20
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#define CORE_DIG_RW_COMMON_15_LANE3_HSTX_WORD_CLK_GATING_OVR_EN_MASK 0x40
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#define CORE_DIG_RW_COMMON_15_LANE3_HSTX_WORD_CLK_GATING_OVR_VAL_MASK 0x80
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#define CORE_DIG_RW_COMMON_15_LANE4_HSTX_WORD_CLK_GATING_OVR_EN_MASK 0x100
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#define CORE_DIG_RW_COMMON_15_LANE4_HSTX_WORD_CLK_GATING_OVR_VAL_MASK 0x200
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#define CORE_DIG_RW_COMMON_15_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_DSK_CLK_MODE_CFG_MASK 0x3
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_LP_DCO_EN_DLY_MASK 0xfc
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_LP_DCO_CLK_EN_DLY_MASK 0x3f00
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_CHOP_CLK_DIV_SEL_MASK 0xc000
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_1_CB_LP_DCO_CLK_EN_DLY_MASK 0x3f
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_1_HSRX_DLY_MASK 0x1c0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_1_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_CB_HSTXLB_DCO_EN_DLY_MASK 0xf
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_CB_HSTXLB_DCO_CLK_EN_DLY_MASK 0xf0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_DLY_MASK 0xf00
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_EN_MASK 0x1000
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_VAL_MASK 0x2000
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_3_HSTX_DIV_EN_CNTR_DLY_MASK 0xff
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#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_3_HIBERNATE_DLY_MASK 0xff00
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#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_DESKEW_FINE_MEM_VALUE_MASK 0x7
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#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_DESKEW_FINE_MEM_ADDR_MASK 0x3f8
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#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_DESKEW_FINE_MEM_WR_EN_MASK 0x400
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#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_COMMON_R_DESKEW_FINE_MEM_DESKEW_FINE_MEM_VALUE_MASK 0x0
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#define CORE_DIG_COMMON_R_DESKEW_FINE_MEM_RESERVED_15_3_MASK 0x0
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_DPHY_LANE0_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_DPHY_LANE0_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_DPHY_LANE0_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_DPHY_LANE0_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_DPHY_LANE0_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_DPHY_LANE0_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_DPHY_LANE0_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_DPHY_LANE0_SPARE_DPHY_LANE_0_SPARE_MASK 0xffff
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_DPHY_LANE1_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_DPHY_LANE1_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_DPHY_LANE1_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_DPHY_LANE1_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_DPHY_LANE1_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_DPHY_LANE1_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_DPHY_LANE1_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_DPHY_LANE1_SPARE_DPHY_LANE_1_SPARE_MASK 0xffff
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_DPHY_LANE2_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_DPHY_LANE2_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_DPHY_LANE2_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_DPHY_LANE2_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_DPHY_LANE2_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_DPHY_LANE2_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_DPHY_LANE2_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_DPHY_LANE2_SPARE_DPHY_LANE_2_SPARE_MASK 0xffff
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_DPHY_LANE3_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_DPHY_LANE3_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_DPHY_LANE3_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_DPHY_LANE3_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_DPHY_LANE3_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_DPHY_LANE3_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_DPHY_LANE3_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_DPHY_LANE3_SPARE_DPHY_LANE_3_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x1
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#define CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x2
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#define CORE_DIG_DLANE_0_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x4
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#define CORE_DIG_DLANE_0_RW_CFG_0_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_BACKWARDS_DESKEW_REG_MASK 0x2
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#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x4
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#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x8
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#define CORE_DIG_DLANE_0_RW_CFG_1_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_DLANE_0_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_DLANE_0_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_DLANE_0_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_TX_0_STATE_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_TX_0_STATE_DCO_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xff00
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#define CORE_DIG_DLANE_0_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_SKEWCAL_REG_MASK 0xff00
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_LATENCY_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_LATENCY_SKEWCAL_REG_MASK 0x18
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_JUMP2STEPS_SKEWCAL_REG_MASK 0x60
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_POLARITY_SKEWCAL_REG_MASK 0x80
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_RECAL_SKEWCAL_REG_MASK 0x100
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1e00
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_SKEWCAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000
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#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x1f8
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#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_SHIFT_STEP_DESKEW_REG_MASK 0xe00
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#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_SHRINK_STEP_DESKEW_REG_MASK 0x7000
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#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_ROUNDUP_DESKEW_REG_MASK 0x8000
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#define CORE_DIG_DLANE_0_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xff00
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#define CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xff00
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_INVORDER_RX_REG_MASK 0x100
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_INITIAL_CALIBRATION_REG_MASK 0x200
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_THSEXIT_MIN_REG_MASK 0x400
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_DESKEW_CNF_REG_MASK 0x1800
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_DESKEW_REARM_INITIAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_0_RW_HS_RX_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_HS_RX_8_HS_RX_8_FILTER_DITHERING_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_0_RW_HS_RX_8_HS_RX_8_START_DELAY_REG_MASK 0x1fe
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#define CORE_DIG_DLANE_0_RW_HS_RX_8_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_0_DESKEWCALDONE_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_0_DESKEWCALFAILED_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_0_DESKEW_CAL_STATUS_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_1_DESKEWCALTIME_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_2_DESKEW_STATE_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_PREV_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_PREV_RESULT_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_CURR_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_FAILED_LEFT_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_FAILED_RIGHT_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_DESKEW_ALL_DIFF_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_3_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_4_EDGE1POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_0_R_HS_RX_4_EDGE2POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_HS_TX_0_HS_TX_0_THSTRAIL_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_1_HS_TX_1_THSZERO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_2_HS_TX_2_TCLKPRE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_INVORDER_TX_REG_MASK 0x100
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x4000
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#define CORE_DIG_DLANE_0_RW_HS_TX_3_HS_TX_3_PIN_SWAP_REG_MASK 0x8000
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#define CORE_DIG_DLANE_0_RW_HS_TX_4_HS_TX_4_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_5_HS_TX_5_THSTRAIL_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_6_HS_TX_6_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_7_HS_TX_7_ALTCALSEED_REG_MASK 0x1ff
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#define CORE_DIG_DLANE_0_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_0_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_VAL_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_0_RW_HS_TX_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_DLANE_0_RW_HS_TX_8_HS_TX_8_TCLKPOST_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_9_HS_TX_9_THSPRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_10_HS_TX_10_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_11_HS_TX_11_TPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_0_RW_HS_TX_12_HS_TX_12_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x1
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#define CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x2
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#define CORE_DIG_DLANE_1_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x4
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#define CORE_DIG_DLANE_1_RW_CFG_0_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_BACKWARDS_DESKEW_REG_MASK 0x2
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#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x4
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#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x8
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#define CORE_DIG_DLANE_1_RW_CFG_1_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_DLANE_1_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_DLANE_1_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_DLANE_1_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_TX_0_STATE_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_TX_0_STATE_DCO_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xff00
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#define CORE_DIG_DLANE_1_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_SKEWCAL_REG_MASK 0xff00
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_LATENCY_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_LATENCY_SKEWCAL_REG_MASK 0x18
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_JUMP2STEPS_SKEWCAL_REG_MASK 0x60
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_POLARITY_SKEWCAL_REG_MASK 0x80
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_RECAL_SKEWCAL_REG_MASK 0x100
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1e00
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_SKEWCAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000
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#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x1f8
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#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_SHIFT_STEP_DESKEW_REG_MASK 0xe00
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#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_SHRINK_STEP_DESKEW_REG_MASK 0x7000
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#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_ROUNDUP_DESKEW_REG_MASK 0x8000
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#define CORE_DIG_DLANE_1_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xff00
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#define CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xff00
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_INVORDER_RX_REG_MASK 0x100
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_INITIAL_CALIBRATION_REG_MASK 0x200
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_THSEXIT_MIN_REG_MASK 0x400
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_DESKEW_CNF_REG_MASK 0x1800
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_DESKEW_REARM_INITIAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_1_RW_HS_RX_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_HS_RX_8_HS_RX_8_FILTER_DITHERING_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_1_RW_HS_RX_8_HS_RX_8_START_DELAY_REG_MASK 0x1fe
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#define CORE_DIG_DLANE_1_RW_HS_RX_8_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_0_DESKEWCALDONE_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_0_DESKEWCALFAILED_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_0_DESKEW_CAL_STATUS_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_1_DESKEWCALTIME_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_2_DESKEW_STATE_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_PREV_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_PREV_RESULT_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_CURR_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_FAILED_LEFT_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_FAILED_RIGHT_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_DESKEW_ALL_DIFF_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_3_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_4_EDGE1POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_1_R_HS_RX_4_EDGE2POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_HS_TX_0_HS_TX_0_THSTRAIL_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_1_HS_TX_1_THSZERO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_2_HS_TX_2_TCLKPRE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_INVORDER_TX_REG_MASK 0x100
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x4000
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#define CORE_DIG_DLANE_1_RW_HS_TX_3_HS_TX_3_PIN_SWAP_REG_MASK 0x8000
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#define CORE_DIG_DLANE_1_RW_HS_TX_4_HS_TX_4_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_5_HS_TX_5_THSTRAIL_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_6_HS_TX_6_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_7_HS_TX_7_ALTCALSEED_REG_MASK 0x1ff
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#define CORE_DIG_DLANE_1_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_1_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_VAL_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_1_RW_HS_TX_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_DLANE_1_RW_HS_TX_8_HS_TX_8_TCLKPOST_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_9_HS_TX_9_THSPRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_10_HS_TX_10_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_11_HS_TX_11_TPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_1_RW_HS_TX_12_HS_TX_12_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x1
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#define CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x2
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#define CORE_DIG_DLANE_2_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x4
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#define CORE_DIG_DLANE_2_RW_CFG_0_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_BACKWARDS_DESKEW_REG_MASK 0x2
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#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x4
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#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x8
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#define CORE_DIG_DLANE_2_RW_CFG_1_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_DLANE_2_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_DLANE_2_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_DLANE_2_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_TX_0_STATE_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_TX_0_STATE_DCO_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xff00
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#define CORE_DIG_DLANE_2_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_SKEWCAL_REG_MASK 0xff00
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_LATENCY_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_LATENCY_SKEWCAL_REG_MASK 0x18
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_JUMP2STEPS_SKEWCAL_REG_MASK 0x60
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_POLARITY_SKEWCAL_REG_MASK 0x80
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_RECAL_SKEWCAL_REG_MASK 0x100
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1e00
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_SKEWCAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000
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#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x1f8
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#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_SHIFT_STEP_DESKEW_REG_MASK 0xe00
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#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_SHRINK_STEP_DESKEW_REG_MASK 0x7000
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#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_ROUNDUP_DESKEW_REG_MASK 0x8000
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#define CORE_DIG_DLANE_2_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xff00
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#define CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xff00
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_INVORDER_RX_REG_MASK 0x100
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_INITIAL_CALIBRATION_REG_MASK 0x200
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_THSEXIT_MIN_REG_MASK 0x400
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_DESKEW_CNF_REG_MASK 0x1800
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_DESKEW_REARM_INITIAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_2_RW_HS_RX_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_HS_RX_8_HS_RX_8_FILTER_DITHERING_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_2_RW_HS_RX_8_HS_RX_8_START_DELAY_REG_MASK 0x1fe
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#define CORE_DIG_DLANE_2_RW_HS_RX_8_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_0_DESKEWCALDONE_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_0_DESKEWCALFAILED_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_0_DESKEW_CAL_STATUS_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_1_DESKEWCALTIME_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_2_DESKEW_STATE_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_PREV_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_PREV_RESULT_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_CURR_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_FAILED_LEFT_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_FAILED_RIGHT_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_DESKEW_ALL_DIFF_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_3_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_4_EDGE1POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_2_R_HS_RX_4_EDGE2POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_HS_TX_0_HS_TX_0_THSTRAIL_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_1_HS_TX_1_THSZERO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_2_HS_TX_2_TCLKPRE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_INVORDER_TX_REG_MASK 0x100
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x4000
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#define CORE_DIG_DLANE_2_RW_HS_TX_3_HS_TX_3_PIN_SWAP_REG_MASK 0x8000
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#define CORE_DIG_DLANE_2_RW_HS_TX_4_HS_TX_4_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_5_HS_TX_5_THSTRAIL_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_6_HS_TX_6_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_7_HS_TX_7_ALTCALSEED_REG_MASK 0x1ff
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#define CORE_DIG_DLANE_2_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_2_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_VAL_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_2_RW_HS_TX_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_DLANE_2_RW_HS_TX_8_HS_TX_8_TCLKPOST_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_9_HS_TX_9_THSPRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_10_HS_TX_10_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_11_HS_TX_11_TPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_2_RW_HS_TX_12_HS_TX_12_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x1
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#define CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x2
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#define CORE_DIG_DLANE_3_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x4
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#define CORE_DIG_DLANE_3_RW_CFG_0_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_BACKWARDS_DESKEW_REG_MASK 0x2
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#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x4
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#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x8
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#define CORE_DIG_DLANE_3_RW_CFG_1_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_DLANE_3_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_DLANE_3_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_DLANE_3_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_TX_0_STATE_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_TX_0_STATE_DCO_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xff00
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#define CORE_DIG_DLANE_3_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_SKEWCAL_REG_MASK 0xff00
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_LATENCY_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_LATENCY_SKEWCAL_REG_MASK 0x18
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_JUMP2STEPS_SKEWCAL_REG_MASK 0x60
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_POLARITY_SKEWCAL_REG_MASK 0x80
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_RECAL_SKEWCAL_REG_MASK 0x100
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1e00
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_SKEWCAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000
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#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x1f8
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#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_SHIFT_STEP_DESKEW_REG_MASK 0xe00
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#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_SHRINK_STEP_DESKEW_REG_MASK 0x7000
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#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_ROUNDUP_DESKEW_REG_MASK 0x8000
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#define CORE_DIG_DLANE_3_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xff00
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#define CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xff00
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_INVORDER_RX_REG_MASK 0x100
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_INITIAL_CALIBRATION_REG_MASK 0x200
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_THSEXIT_MIN_REG_MASK 0x400
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_DESKEW_CNF_REG_MASK 0x1800
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_DESKEW_REARM_INITIAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_3_RW_HS_RX_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_HS_RX_8_HS_RX_8_FILTER_DITHERING_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_3_RW_HS_RX_8_HS_RX_8_START_DELAY_REG_MASK 0x1fe
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#define CORE_DIG_DLANE_3_RW_HS_RX_8_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_0_DESKEWCALDONE_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_0_DESKEWCALFAILED_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_0_DESKEW_CAL_STATUS_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_1_DESKEWCALTIME_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_2_DESKEW_STATE_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_PREV_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_PREV_RESULT_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_CURR_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_FAILED_LEFT_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_FAILED_RIGHT_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_DESKEW_ALL_DIFF_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_3_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_4_EDGE1POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_3_R_HS_RX_4_EDGE2POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_HS_TX_0_HS_TX_0_THSTRAIL_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_1_HS_TX_1_THSZERO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_2_HS_TX_2_TCLKPRE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_INVORDER_TX_REG_MASK 0x100
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x4000
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#define CORE_DIG_DLANE_3_RW_HS_TX_3_HS_TX_3_PIN_SWAP_REG_MASK 0x8000
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#define CORE_DIG_DLANE_3_RW_HS_TX_4_HS_TX_4_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_5_HS_TX_5_THSTRAIL_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_6_HS_TX_6_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_7_HS_TX_7_ALTCALSEED_REG_MASK 0x1ff
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#define CORE_DIG_DLANE_3_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_3_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_VAL_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_3_RW_HS_TX_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_DLANE_3_RW_HS_TX_8_HS_TX_8_TCLKPOST_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_9_HS_TX_9_THSPRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_10_HS_TX_10_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_11_HS_TX_11_TPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_3_RW_HS_TX_12_HS_TX_12_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x1
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#define CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x2
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#define CORE_DIG_DLANE_CLK_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x4
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#define CORE_DIG_DLANE_CLK_RW_CFG_0_RESERVED_15_3_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_CFG_1_CFG_1_PREAMBLE_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_CLK_RW_CFG_1_CFG_1_BACKWARDS_DESKEW_REG_MASK 0x2
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#define CORE_DIG_DLANE_CLK_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x4
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#define CORE_DIG_DLANE_CLK_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x8
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#define CORE_DIG_DLANE_CLK_RW_CFG_1_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_DLANE_CLK_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_DLANE_CLK_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_TX_0_STATE_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_TX_0_STATE_DCO_DHSTX_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xff00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_SKEWCAL_REG_MASK 0xff00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_LATENCY_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_LATENCY_SKEWCAL_REG_MASK 0x18
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_JUMP2STEPS_SKEWCAL_REG_MASK 0x60
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_POLARITY_SKEWCAL_REG_MASK 0x80
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_RECAL_SKEWCAL_REG_MASK 0x100
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1e00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_SKEWCAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x7
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x1f8
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_3_HS_RX_3_SHIFT_STEP_DESKEW_REG_MASK 0xe00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_3_HS_RX_3_SHRINK_STEP_DESKEW_REG_MASK 0x7000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_3_HS_RX_3_ROUNDUP_DESKEW_REG_MASK 0x8000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xff00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xff00
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_INVORDER_RX_REG_MASK 0x100
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_INITIAL_CALIBRATION_REG_MASK 0x200
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_THSEXIT_MIN_REG_MASK 0x400
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_DESKEW_CNF_REG_MASK 0x1800
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_DESKEW_REARM_INITIAL_REG_MASK 0x4000
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_8_HS_RX_8_FILTER_DITHERING_EN_REG_MASK 0x1
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_8_HS_RX_8_START_DELAY_REG_MASK 0x1fe
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#define CORE_DIG_DLANE_CLK_RW_HS_RX_8_RESERVED_15_9_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_0_DESKEWCALDONE_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_0_DESKEWCALFAILED_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_0_DESKEW_CAL_STATUS_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_1_DESKEWCALTIME_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_2_DESKEW_STATE_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_2_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_PREV_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_PREV_RESULT_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_CURR_ACTION_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_FAILED_LEFT_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_FAILED_RIGHT_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_DESKEW_ALL_DIFF_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_3_RESERVED_15_12_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_4_EDGE1POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_CLK_R_HS_RX_4_EDGE2POINTER_SKEWCAL_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_0_HS_TX_0_THSTRAIL_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_1_HS_TX_1_THSZERO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_2_HS_TX_2_TCLKPRE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_INVORDER_TX_REG_MASK 0x100
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x4000
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_3_HS_TX_3_PIN_SWAP_REG_MASK 0x8000
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_4_HS_TX_4_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_5_HS_TX_5_THSTRAIL_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_6_HS_TX_6_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_7_HS_TX_7_ALTCALSEED_REG_MASK 0x1ff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_EN_REG_MASK 0x200
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_7_HS_TX_7_STATE_DCO_OVR_VAL_REG_MASK 0x3c00
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_7_RESERVED_15_14_MASK 0x0
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_8_HS_TX_8_TCLKPOST_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_9_HS_TX_9_THSPRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_10_HS_TX_10_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_11_HS_TX_11_TPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_DLANE_CLK_RW_HS_TX_12_HS_TX_12_THSEXIT_DCO_REG_MASK 0xffff
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_CPHY_TRIO0_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_CPHY_TRIO0_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_CPHY_TRIO0_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_CPHY_TRIO0_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_CPHY_TRIO0_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_CPHY_TRIO0_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_CPHY_TRIO0_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_CPHY_TRIO0_SPARE_CPHY_TRIO0_SPARE_MASK 0xffff
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_CPHY_TRIO1_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_CPHY_TRIO1_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_CPHY_TRIO1_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_CPHY_TRIO1_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_CPHY_TRIO1_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_CPHY_TRIO1_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_CPHY_TRIO1_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_CPHY_TRIO1_SPARE_CPHY_TRIO1_SPARE_MASK 0xffff
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PM_MODE_MASK 0xf
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PM_START_OVR_VAL_MASK 0x10
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PM_START_OVR_EN_MASK 0x20
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_VAL_MASK 0x40
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PM_SAMPLE_COUNTER_OVR_EN_MASK 0x80
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PG_MODE_MASK 0xf00
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PG_START_OVR_VAL_MASK 0x1000
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PG_START_OVR_EN_MASK 0x2000
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#define PPI_RW_CPHY_TRIO2_LBERT_0_LBERT_PG_ERROR_INJECTION_MASK 0x4000
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#define PPI_RW_CPHY_TRIO2_LBERT_0_RESERVED_15_15_MASK 0x0
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#define PPI_RW_CPHY_TRIO2_LBERT_1_LBERT_PG_USER_PATTERN_MASK 0xff
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#define PPI_RW_CPHY_TRIO2_LBERT_1_RESERVED_15_8_MASK 0x0
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#define PPI_R_CPHY_TRIO2_LBERT_0_LBERT_PM_ERROR_COUNTER_MASK 0x0
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#define PPI_R_CPHY_TRIO2_LBERT_1_LBERT_PG_ENABLED_MASK 0x0
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#define PPI_R_CPHY_TRIO2_LBERT_1_RESERVED_15_1_MASK 0x0
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#define PPI_RW_CPHY_TRIO2_SPARE_CPHY_TRIO2_SPARE_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x7
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x8
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_HS_ORDER_SWAP_REG_MASK 0x10
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_HS_DECODE_SWAP_REG_MASK 0x20
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_HS_ALIGNER_SWAP_REG_MASK 0x40
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_HS_SYNC_DET_SWAP_REG_MASK 0x80
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_ALP_ENABLE_REG_MASK 0x100
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#define CORE_DIG_CLANE_0_RW_CFG_0_CFG_0_SWAP_ENCODE_REG_MASK 0x200
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#define CORE_DIG_CLANE_0_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x400
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#define CORE_DIG_CLANE_0_RW_CFG_0_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_CLANE_0_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_CLANE_0_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_CLANE_0_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_CLANE_0_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_CLANE_0_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_CLANE_0_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_CLANE_0_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_RX_0_HS_RX_0_HS_CDR_UPDATE_SETTINGS_REG_MASK 0x1
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#define CORE_DIG_CLANE_0_RW_HS_RX_0_HS_RX_0_HS_CDR_FEEDBACK_ENABLED_REG_MASK 0x2
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#define CORE_DIG_CLANE_0_RW_HS_RX_0_HSACTIVERX_DLY_REG_MASK 0x7c
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#define CORE_DIG_CLANE_0_RW_HS_RX_0_HSRX_CPHY_CDR_FBK_EN_DLY_REG_MASK 0x380
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#define CORE_DIG_CLANE_0_RW_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_RX_1_HS_RX_1_HS_CDR_TIMEBASE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_RX_2_HS_RX_2_HS_CDR_COARSE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_REG_MASK 0x1
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#define CORE_DIG_CLANE_0_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_DLY_REG_MASK 0x7e
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#define CORE_DIG_CLANE_0_RW_HS_RX_3_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_RX_4_HS_RX_3_HS_CDR_COARSE_OBS_SEL_REG_MASK 0xf
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#define CORE_DIG_CLANE_0_RW_HS_RX_4_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_RX_5_HS_RX_5_HS_CDR_INIT_WAIT_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_RX_6_HS_RX_6_HS_CDR_STUCK_THRESH_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_R_RX_0_O_CDR_CALDONE_MASK 0x0
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#define CORE_DIG_CLANE_0_R_RX_0_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_0_R_RX_1_COARSE_DIF_TARGET_MASK 0x0
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#define CORE_DIG_CLANE_0_R_TX_0_STATE_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_0_R_TX_0_STATE_DCO_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_0_R_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_CLANE_0_R_RX_2_CR_COARSE_VALUE_OBS_MASK 0x0
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#define CORE_DIG_CLANE_0_R_RX_3_CR_CDR_STATUS_OBS_MASK 0x0
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#define CORE_DIG_CLANE_0_R_RX_3_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_TX_0_HS_TX_0_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_1_HS_TX_1_TPOST_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_2_HS_TX_2_TCALPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0xf
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x10
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_BURST_TYPE_REG_MASK 0xe0
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x100
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_INVORDER_REG_MASK 0x200
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_STATE_DCO_VR_EN_REG_MASK 0x400
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_HS_TX_3_STATE_DCO_OVR_VAL_REG_MASK 0x7800
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#define CORE_DIG_CLANE_0_RW_HS_TX_3_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB0_REG_MASK 0x7
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB1_REG_MASK 0x38
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB2_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB3_REG_MASK 0xe00
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB4_REG_MASK 0x7000
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#define CORE_DIG_CLANE_0_RW_HS_TX_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB5_REG_MASK 0x7
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB6_REG_MASK 0x38
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB7_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB8_REG_MASK 0xe00
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB9_REG_MASK 0x7000
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#define CORE_DIG_CLANE_0_RW_HS_TX_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB10_REG_MASK 0x7
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB11_REG_MASK 0x38
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB12_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB13_REG_MASK 0xe00
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_HS_TX_6_PIN_SWAP_REG_MASK 0x7000
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#define CORE_DIG_CLANE_0_RW_HS_TX_6_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_0_RW_HS_TX_7_HS_TX_7_T3PRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_8_HS_TX_8_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_9_HS_TX_9_T3POST_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_10_HS_TX_10_TPREBEGIN_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_11_HS_TX_11_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_12_HS_TX_12_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_0_RW_HS_TX_13_HS_TX_13_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_CLANE_0_RW_HS_TX_13_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x7
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x8
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_HS_ORDER_SWAP_REG_MASK 0x10
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_HS_DECODE_SWAP_REG_MASK 0x20
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_HS_ALIGNER_SWAP_REG_MASK 0x40
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_HS_SYNC_DET_SWAP_REG_MASK 0x80
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_ALP_ENABLE_REG_MASK 0x100
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#define CORE_DIG_CLANE_1_RW_CFG_0_CFG_0_SWAP_ENCODE_REG_MASK 0x200
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#define CORE_DIG_CLANE_1_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x400
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#define CORE_DIG_CLANE_1_RW_CFG_0_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_CLANE_1_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_CLANE_1_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_CLANE_1_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_CLANE_1_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_CLANE_1_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_CLANE_1_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_CLANE_1_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_RX_0_HS_RX_0_HS_CDR_UPDATE_SETTINGS_REG_MASK 0x1
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#define CORE_DIG_CLANE_1_RW_HS_RX_0_HS_RX_0_HS_CDR_FEEDBACK_ENABLED_REG_MASK 0x2
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#define CORE_DIG_CLANE_1_RW_HS_RX_0_HSACTIVERX_DLY_REG_MASK 0x7c
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#define CORE_DIG_CLANE_1_RW_HS_RX_0_HSRX_CPHY_CDR_FBK_EN_DLY_REG_MASK 0x380
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#define CORE_DIG_CLANE_1_RW_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_RX_1_HS_RX_1_HS_CDR_TIMEBASE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_RX_2_HS_RX_2_HS_CDR_COARSE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_REG_MASK 0x1
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#define CORE_DIG_CLANE_1_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_DLY_REG_MASK 0x7e
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#define CORE_DIG_CLANE_1_RW_HS_RX_3_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_RX_4_HS_RX_3_HS_CDR_COARSE_OBS_SEL_REG_MASK 0xf
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#define CORE_DIG_CLANE_1_RW_HS_RX_4_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_RX_5_HS_RX_5_HS_CDR_INIT_WAIT_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_RX_6_HS_RX_6_HS_CDR_STUCK_THRESH_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_R_RX_0_O_CDR_CALDONE_MASK 0x0
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#define CORE_DIG_CLANE_1_R_RX_0_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_1_R_RX_1_COARSE_DIF_TARGET_MASK 0x0
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#define CORE_DIG_CLANE_1_R_TX_0_STATE_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_1_R_TX_0_STATE_DCO_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_1_R_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_CLANE_1_R_RX_2_CR_COARSE_VALUE_OBS_MASK 0x0
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#define CORE_DIG_CLANE_1_R_RX_3_CR_CDR_STATUS_OBS_MASK 0x0
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#define CORE_DIG_CLANE_1_R_RX_3_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_TX_0_HS_TX_0_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_1_HS_TX_1_TPOST_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_2_HS_TX_2_TCALPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0xf
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x10
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_BURST_TYPE_REG_MASK 0xe0
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x100
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_INVORDER_REG_MASK 0x200
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_STATE_DCO_VR_EN_REG_MASK 0x400
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_HS_TX_3_STATE_DCO_OVR_VAL_REG_MASK 0x7800
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#define CORE_DIG_CLANE_1_RW_HS_TX_3_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB0_REG_MASK 0x7
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB1_REG_MASK 0x38
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB2_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB3_REG_MASK 0xe00
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB4_REG_MASK 0x7000
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#define CORE_DIG_CLANE_1_RW_HS_TX_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB5_REG_MASK 0x7
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB6_REG_MASK 0x38
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB7_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB8_REG_MASK 0xe00
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB9_REG_MASK 0x7000
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#define CORE_DIG_CLANE_1_RW_HS_TX_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB10_REG_MASK 0x7
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB11_REG_MASK 0x38
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB12_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB13_REG_MASK 0xe00
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_HS_TX_6_PIN_SWAP_REG_MASK 0x7000
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#define CORE_DIG_CLANE_1_RW_HS_TX_6_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_1_RW_HS_TX_7_HS_TX_7_T3PRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_8_HS_TX_8_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_9_HS_TX_9_T3POST_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_10_HS_TX_10_TPREBEGIN_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_11_HS_TX_11_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_12_HS_TX_12_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_1_RW_HS_TX_13_HS_TX_13_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_CLANE_1_RW_HS_TX_13_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x7
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x8
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_HS_ORDER_SWAP_REG_MASK 0x10
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_HS_DECODE_SWAP_REG_MASK 0x20
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_HS_ALIGNER_SWAP_REG_MASK 0x40
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_HS_SYNC_DET_SWAP_REG_MASK 0x80
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_ALP_ENABLE_REG_MASK 0x100
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#define CORE_DIG_CLANE_2_RW_CFG_0_CFG_0_SWAP_ENCODE_REG_MASK 0x200
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#define CORE_DIG_CLANE_2_RW_CFG_0_LOOPBACK_MODE_EN_MASK 0x400
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#define CORE_DIG_CLANE_2_RW_CFG_0_RESERVED_15_11_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_CFG_2_CFG_2_SPARE_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_LP_0_LP_0_TTAGET_REG_MASK 0xf
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#define CORE_DIG_CLANE_2_RW_LP_0_LP_0_TTASURE_REG_MASK 0xf0
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#define CORE_DIG_CLANE_2_RW_LP_0_LP_0_TTAGO_REG_MASK 0xf00
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#define CORE_DIG_CLANE_2_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xf000
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#define CORE_DIG_CLANE_2_RW_LP_1_LP_1_ERRCONTENTION_THRES_REG_MASK 0xff
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#define CORE_DIG_CLANE_2_RW_LP_1_LP_1_LPTX_PON_TIMER_REG_MASK 0xff00
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#define CORE_DIG_CLANE_2_R_LP_0_LP_0_HSACTIVERX_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_0_LP_0_RXHSRQST_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_0_RESERVED_15_2_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_1_LP_1_STATE_BTA_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_1_LP_1_STATE_LPRX_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_1_LP_1_STATE_LPTX_MASK 0x0
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#define CORE_DIG_CLANE_2_R_LP_1_RESERVED_15_13_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_RX_0_HS_RX_0_HS_CDR_UPDATE_SETTINGS_REG_MASK 0x1
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#define CORE_DIG_CLANE_2_RW_HS_RX_0_HS_RX_0_HS_CDR_FEEDBACK_ENABLED_REG_MASK 0x2
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#define CORE_DIG_CLANE_2_RW_HS_RX_0_HSACTIVERX_DLY_REG_MASK 0x7c
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#define CORE_DIG_CLANE_2_RW_HS_RX_0_HSRX_CPHY_CDR_FBK_EN_DLY_REG_MASK 0x380
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#define CORE_DIG_CLANE_2_RW_HS_RX_0_RESERVED_15_10_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_RX_1_HS_RX_1_HS_CDR_TIMEBASE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_RX_2_HS_RX_2_HS_CDR_COARSE_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_REG_MASK 0x1
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#define CORE_DIG_CLANE_2_RW_HS_RX_3_HSRX_CPHY_CDR_FBK_FAST_LOCK_EN_DLY_REG_MASK 0x7e
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#define CORE_DIG_CLANE_2_RW_HS_RX_3_RESERVED_15_7_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_RX_4_HS_RX_3_HS_CDR_COARSE_OBS_SEL_REG_MASK 0xf
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#define CORE_DIG_CLANE_2_RW_HS_RX_4_RESERVED_15_4_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_RX_5_HS_RX_5_HS_CDR_INIT_WAIT_TARGET_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_RX_6_HS_RX_6_HS_CDR_STUCK_THRESH_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_R_RX_0_O_CDR_CALDONE_MASK 0x0
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#define CORE_DIG_CLANE_2_R_RX_0_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_2_R_RX_1_COARSE_DIF_TARGET_MASK 0x0
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#define CORE_DIG_CLANE_2_R_TX_0_STATE_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_2_R_TX_0_STATE_DCO_CHSTX_MASK 0x0
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#define CORE_DIG_CLANE_2_R_TX_0_RESERVED_15_8_MASK 0x0
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#define CORE_DIG_CLANE_2_R_RX_2_CR_COARSE_VALUE_OBS_MASK 0x0
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#define CORE_DIG_CLANE_2_R_RX_3_CR_CDR_STATUS_OBS_MASK 0x0
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#define CORE_DIG_CLANE_2_R_RX_3_RESERVED_15_1_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_TX_0_HS_TX_0_THSEXIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_1_HS_TX_1_TPOST_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_2_HS_TX_2_TCALPREAMBLE_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_STATE_OVR_REG_MASK 0xf
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_STATE_OVR_EN_REG_MASK 0x10
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_BURST_TYPE_REG_MASK 0xe0
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_HSDIRECT_REG_MASK 0x100
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_INVORDER_REG_MASK 0x200
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_STATE_DCO_VR_EN_REG_MASK 0x400
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_HS_TX_3_STATE_DCO_OVR_VAL_REG_MASK 0x7800
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#define CORE_DIG_CLANE_2_RW_HS_TX_3_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB0_REG_MASK 0x7
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB1_REG_MASK 0x38
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB2_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB3_REG_MASK 0xe00
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_HS_TX_4_PROGSEQSYMB4_REG_MASK 0x7000
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#define CORE_DIG_CLANE_2_RW_HS_TX_4_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB5_REG_MASK 0x7
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB6_REG_MASK 0x38
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB7_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB8_REG_MASK 0xe00
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_HS_TX_5_PROGSEQSYMB9_REG_MASK 0x7000
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#define CORE_DIG_CLANE_2_RW_HS_TX_5_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB10_REG_MASK 0x7
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB11_REG_MASK 0x38
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB12_REG_MASK 0x1c0
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_HS_TX_6_PROGSEQSYMB13_REG_MASK 0xe00
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_HS_TX_6_PIN_SWAP_REG_MASK 0x7000
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#define CORE_DIG_CLANE_2_RW_HS_TX_6_RESERVED_15_15_MASK 0x0
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#define CORE_DIG_CLANE_2_RW_HS_TX_7_HS_TX_7_T3PRPR_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_8_HS_TX_8_TLP11END_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_9_HS_TX_9_T3POST_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_10_HS_TX_10_TPREBEGIN_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_11_HS_TX_11_TLPX_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_12_HS_TX_12_TLP11INIT_DCO_REG_MASK 0xffff
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#define CORE_DIG_CLANE_2_RW_HS_TX_13_HS_TX_13_TLPTXOVERLAP_REG_MASK 0xff
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#define CORE_DIG_CLANE_2_RW_HS_TX_13_RESERVED_15_8_MASK 0x0
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#endif /* _MTK_MT6382_H */
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