292 lines
10 KiB
C
292 lines
10 KiB
C
/*
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* s2mu004-muic-hv.h - MUIC for the Samsung s2mu004
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*
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* Copyright (C) 2015 Samsung Electrnoics
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on max77843-muic.h
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*
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*/
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#ifndef __S2MU004_MUIC_HV_H__
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#define __S2MU004_MUIC_HV_H__
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#define MUIC_HV_DEV_NAME "muic-s2mu004-hv"
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enum s2mu004_reg_bit_control {
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S2MU004_DISABLE_BIT = 0,
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S2MU004_ENABLE_BIT,
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};
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/* S2MU004 AFC INTMASK register */
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#define INTMASK_VBADCM_SHIFT 0
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#define INTMASK_VDNMONM_SHIFT 1
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#define INTMASK_DNRESM_SHIFT 2
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#define INTMASK_MPNACKM_SHIFT 3
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#define INTMASK_MRXBUFOWM_SHIFT 4
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#define INTMASK_MRXTRFM_SHIFT 5
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#define INTMASK_MRXPERRM_SHIFT 6
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#define INTMASK_MRXRDYM_SHIFT 7
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#define INTMASK_VBADCM_MASK (S2MU004_ENABLE_BIT << INTMASK_VBADCM_SHIFT)
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#define INTMASK_VDNMONM_MASK (S2MU004_ENABLE_BIT << INTMASK_VDNMONM_SHIFT)
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#define INTMASK_DNRESM_MASK (S2MU004_ENABLE_BIT << INTMASK_DNRESM_SHIFT)
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#define INTMASK_MPNACKM_MASK (S2MU004_ENABLE_BIT << INTMASK_MPNACKM_SHIFT)
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#define INTMASK_MRXBUFOWM_MASK (S2MU004_ENABLE_BIT << INTMASK_MRXBUFOWM_SHIFT)
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#define INTMASK_MRXTRFM_MASK (S2MU004_ENABLE_BIT << INTMASK_MRXTRFM_SHIFT)
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#define INTMASK_MRXPERRM_MASK (S2MU004_ENABLE_BIT << INTMASK_MRXPERRM_SHIFT)
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#define INTMASK_MRXRDYM_MASK (S2MU004_ENABLE_BIT << INTMASK_MRXRDYM_SHIFT)
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/* S2MU004 AFC STATUS register */
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#define STATUS_VBADC_SHIFT 0
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#define STATUS_VDNMON_SHIFT 4
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#define STATUS_DNRES_SHIFT 5
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#define STATUS_MPNACK_SHIFT 6
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#define STATUS_VBADC_MASK (0xf << STATUS_VBADC_SHIFT)
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#define STATUS_VDNMON_MASK (0x1 << STATUS_VDNMON_SHIFT)
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#define STATUS_DNRES_MASK (0x1 << STATUS_DNRES_SHIFT)
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#define STATUS_MPNACK_MASK (0x1 << STATUS_MPNACK_SHIFT)
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/* S2MU004 HVCONTROL1 register */
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#define HVCONTROL1_DPDNVDEN_SHIFT 0
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#define HVCONTROL1_DNVD_SHIFT 1
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#define HVCONTROL1_DPVD_SHIFT 3
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#define HVCONTROL1_VBUSADCEN_SHIFT 5
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#define HVCONTROL1_CTRLIDMON_SHIFT 6
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#define HVCONTROL1_AFCEN_SHIFT 7
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#define HVCONTROL1_DPDNVDEN_MASK (0x1 << HVCONTROL1_DPDNVDEN_SHIFT)
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#define HVCONTROL1_DNVD_MASK (0x3 << HVCONTROL1_DNVD_SHIFT)
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#define HVCONTROL1_DPVD_MASK (0x3 << HVCONTROL1_DPVD_SHIFT)
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#define HVCONTROL1_VBUSADCEN_MASK (0x1 << HVCONTROL1_VBUSADCEN_SHIFT)
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#define HVCONTROL1_CTRLIDMON_MASK (0x1 << HVCONTROL1_CTRLIDMON_SHIFT)
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#define HVCONTROL1_AFCEN_MASK (0x1 << HVCONTROL1_AFCEN_SHIFT)
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/* S2MU004 HVCONTROL2 register */
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//#define HVCONTROL2_HVDIGEN_SHIFT 0
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#define HVCONTROL2_DP06EN_SHIFT 1
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#define HVCONTROL2_DNRESEN_SHIFT 2
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#define HVCONTROL2_MPING_SHIFT 3
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#define HVCONTROL2_MTXEN_SHIFT 4
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#define HVCONTROL2_RSTDM100UI_SHIFT 7
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//#define HVCONTROL2_MTXBUSRES_SHIFT 5
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//#define HVCONTROL2_MPNGENB_SHIFT 6
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//#define HVCONTROL2_HVDIGEN_MASK (0x1 << HVCONTROL2_HVDIGEN_SHIFT)
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#define HVCONTROL2_DP06EN_MASK (0x1 << HVCONTROL2_DP06EN_SHIFT)
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#define HVCONTROL2_DNRESEN_MASK (0x1 << HVCONTROL2_DNRESEN_SHIFT)
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#define HVCONTROL2_MPING_MASK (0x1 << HVCONTROL2_MPING_SHIFT)
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#define HVCONTROL2_MTXEN_MASK (0x1 << HVCONTROL2_MTXEN_SHIFT)
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#define HVCONTROL2_RSTDM100UI_MASK (0x1 << HVCONTROL2_RSTDM100UI_SHIFT)
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//#define HVCONTROL2_MTXBUSRES_MASK (0x1 << HVCONTROL2_MTXBUSRES_SHIFT)
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//#define HVCONTROL2_MPNGENB_MASK (0x1 << HVCONTROL2_MPNGENB_SHIFT)
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#define HVTXBYTE_5V 0x0
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#define HVTXBYTE_6V 0x1
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#define HVTXBYTE_7V 0x2
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#define HVTXBYTE_8V 0x3
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#define HVTXBYTE_9V 0x4
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#define HVTXBYTE_10V 0x5
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#define HVTXBYTE_11V 0x6
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#define HVTXBYTE_12V 0x7
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#define HVTXBYTE_13V 0x8
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#define HVTXBYTE_14V 0x9
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#define HVTXBYTE_15V 0xA
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#define HVTXBYTE_16V 0xB
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#define HVTXBYTE_17V 0xC
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#define HVTXBYTE_18V 0xD
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#define HVTXBYTE_19V 0xE
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#define HVTXBYTE_20V 0xF
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#define HVTXBYTE_0_75A 0x0
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#define HVTXBYTE_0_90A 0x1
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#define HVTXBYTE_1_05A 0x2
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#define HVTXBYTE_1_20A 0x3
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#define HVTXBYTE_1_35A 0x4
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#define HVTXBYTE_1_50A 0x5
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#define HVTXBYTE_1_65A 0x6
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#define HVTXBYTE_1_80A 0x7
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#define HVTXBYTE_1_95A 0x8
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#define HVTXBYTE_2_10A 0x9
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#define HVTXBYTE_2_25A 0xA
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#define HVTXBYTE_2_40A 0xB
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#define HVTXBYTE_2_55A 0xC
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#define HVTXBYTE_2_70A 0xD
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#define HVTXBYTE_2_85A 0xE
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#define HVTXBYTE_3_00A 0xF
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/* S2MU004 HVRXBYTE register */
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#define HVRXBYTE_MAX 16
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/* S2MU004 AFC charger W/A Check NUM */
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#define AFC_CHARGER_WA_PING 5
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/* S2MU004 MPing miss SW Workaround - delay time */
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#define MPING_MISS_WA_TIME 2000
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#define MUIC_HV_5V 0x08
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#define MUIC_HV_9V 0x46
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#if 0
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typedef enum {
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DPDNVDEN_DISABLE = 0x00,
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DPDNVDEN_ENABLE = (0x1 << HVCONTROL1_DPDNVDEN_SHIFT),
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DPDNVDEN_DONTCARE = 0xff,
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} dpdnvden_t;
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#endif
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typedef enum {
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VDNMON_LOW = 0x00,
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VDNMON_HIGH = (0x1 << STATUS_VDNMON_SHIFT),
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VDNMON_DONTCARE = 0xff,
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} vdnmon_t;
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typedef enum {
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// VBADC_VBDET = 0x00,
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VBADC_5_3V = 0x00,
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VBADC_5_7V_6_3V = (0x1 << STATUS_VBADC_SHIFT),
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VBADC_6_7V_7_3V = (0x2 << STATUS_VBADC_SHIFT),
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VBADC_7_7V_8_3V = (0x3 << STATUS_VBADC_SHIFT),
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VBADC_8_7V_9_3V = (0x4 << STATUS_VBADC_SHIFT),
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VBADC_9_7V_10_3V = (0x5 << STATUS_VBADC_SHIFT),
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VBADC_10_7V_11_3V = (0x6 << STATUS_VBADC_SHIFT),
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VBADC_11_7V_12_3V = (0x7 << STATUS_VBADC_SHIFT),
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VBADC_12_7V_13_3V = (0x8 << STATUS_VBADC_SHIFT),
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VBADC_13_7V_14_3V = (0x9 << STATUS_VBADC_SHIFT),
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VBADC_14_7V_15_3V = (0xA << STATUS_VBADC_SHIFT),
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VBADC_15_7V_16_3V = (0xB << STATUS_VBADC_SHIFT),
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VBADC_16_7V_17_3V = (0xC << STATUS_VBADC_SHIFT),
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VBADC_17_7V_18_3V = (0xD << STATUS_VBADC_SHIFT),
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VBADC_18_7V_19_3V = (0xE << STATUS_VBADC_SHIFT),
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VBADC_19_7V = (0xF << STATUS_VBADC_SHIFT),
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// VBADC_QC_5V = 0xeb,
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// VBADC_QC_9V = 0xec,
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// VBADC_QC_12V = 0xed,
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// VBADC_QC_20V = 0xee,
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VBADC_AFC_5V = 0xfa,
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VBADC_AFC_9V = 0xfb,
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VBADC_QC_9V = 0xfb,
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VBADC_AFC_ERR_V = 0xfc,
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VBADC_AFC_ERR_V_NOT_0 = 0xfd,
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VBADC_ANY = 0xfe,
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VBADC_DONTCARE = 0xff,
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} vbadc_t;
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#if 0
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enum {
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HV_SUPPORT_QC_5V = 5,
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HV_SUPPORT_QC_9V = 9,
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HV_SUPPORT_QC_12V = 12,
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HV_SUPPORT_QC_20V = 20,
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};
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#endif
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/* MUIC afc irq type */
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typedef enum {
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MUIC_AFC_IRQ_VDNMON = 0,
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MUIC_AFC_IRQ_MRXRDY,
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MUIC_AFC_IRQ_VBADC,
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MUIC_AFC_IRQ_MPNACK,
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MUIC_AFC_IRQ_DONTCARE = 0xff,
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} muic_afc_irq_t;
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/* muic chip specific internal data structure */
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typedef struct s2mu004_muic_afc_data {
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muic_attached_dev_t new_dev;
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const char *afc_name;
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muic_afc_irq_t afc_irq;
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// u8 hvcontrol1_dpdnvden;
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u8 status_vbadc;
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u8 status_vdnmon;
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int function_num;
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struct s2mu004_muic_afc_data *next;
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} muic_afc_data_t;
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enum s2mu004_reg_hv_val {
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#if 0
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S2MU004_MUIC_HVCONTROL1_DPVD_06 = (0x2 << HVCONTROL1_DPVD_SHIFT),
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S2MU004_MUIC_HVCONTROL1_11 = (S2MU004_MUIC_HVCONTROL1_DPVD_06 |
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HVCONTROL1_DPDNVDEN_MASK),
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S2MU004_MUIC_HVCONTROL1_31 = (HVCONTROL1_VBUSADCEN_MASK |
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S2MU004_MUIC_HVCONTROL1_DPVD_06 |
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HVCONTROL1_DPDNVDEN_MASK),
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S2MU004_MUIC_HVCONTROL2_06 = (HVCONTROL2_DP06EN_MASK | HVCONTROL2_DNRESEN_MASK),
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S2MU004_MUIC_HVCONTROL2_13 = (HVCONTROL2_MTXEN_MASK | HVCONTROL2_DP06EN_MASK |
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HVCONTROL2_HVDIGEN_MASK),
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S2MU004_MUIC_HVCONTROL2_1B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK |
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HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
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S2MU004_MUIC_HVCONTROL2_1F = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK |
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HVCONTROL2_DNRESEN_MASK | HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
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S2MU004_MUIC_HVCONTROL2_5B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK |
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HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK | HVCONTROL2_MPNGENB_MASK),
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S2MU004_MUIC_INTMASK3_FB = (INTMASK3_MRXRDYM_MASK | INTMASK3_MRXPERRM_MASK |
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INTMASK3_MRXTRFM_MASK | INTMASK3_MRXBUFOWM_MASK |
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INTMASK3_MPNACKM_MASK | INTMASK3_VDNMONM_MASK |
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INTMASK3_VBADCM_MASK),
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#endif
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S2MU004_MUIC_HVCONTROL1_A0 = (HVCONTROL1_AFCEN_MASK |
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HVCONTROL1_VBUSADCEN_MASK),
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S2MU004_MUIC_HVCONTROL2_06 = (HVCONTROL2_DNRESEN_MASK |
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HVCONTROL2_DP06EN_MASK),
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S2MU004_MUIC_HVCONTROL1_E0 = (HVCONTROL1_AFCEN_MASK | HVCONTROL1_CTRLIDMON_MASK |
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HVCONTROL1_VBUSADCEN_MASK),
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S2MU004_MUIC_HVCONTROL2_0E = (HVCONTROL2_MPING_MASK | HVCONTROL2_DNRESEN_MASK |
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HVCONTROL2_DP06EN_MASK),
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};
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struct s2mu004_muic_data;
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extern int s2mu004_muic_reset_afc_register(struct s2mu004_muic_data *muic_data);
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extern bool muic_check_dev_ta(struct s2mu004_muic_data *muic_data);
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extern bool muic_check_is_hv_dev(struct s2mu004_muic_data *muic_data);
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extern muic_attached_dev_t hv_muic_check_id_err
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(struct s2mu004_muic_data *muic_data, muic_attached_dev_t new_dev);
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extern void s2mu004_hv_muic_reset_hvcontrol_reg(struct s2mu004_muic_data *muic_data);
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#if defined(CONFIG_OF)
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extern int of_s2mu004_hv_muic_dt(struct s2mu004_muic_data *muic_data);
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#endif
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extern int s2mu004_afc_muic_irq_init(struct s2mu004_muic_data *muic_data);
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extern void s2mu004_hv_muic_free_irqs(struct s2mu004_muic_data *muic_data);
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extern int s2mu004_muic_hv_update_reg(struct i2c_client *i2c,
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const u8 reg, const u8 val, const u8 mask, const bool debug_en);
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extern void s2mu004_muic_set_afc_ready(struct s2mu004_muic_data *muic_data, bool value);
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extern void s2mu004_hv_muic_init_check_dpdnvden(struct s2mu004_muic_data *muic_data);
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extern void s2mu004_hv_muic_init_detect(struct s2mu004_muic_data *muic_data);
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extern void s2mu004_hv_muic_initialize(struct s2mu004_muic_data *muic_data);
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extern void s2mu004_hv_muic_remove(struct s2mu004_muic_data *muic_data);
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//extern void s2mu004_hv_muic_remove_wo_free_irq(struct s2mu004_muic_data *muic_data);
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#if 0
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extern void s2mu004_muic_set_adcmode_always(struct s2mu004_muic_data *muic_data);
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#if !defined(CONFIG_SEC_FACTORY)
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extern void s2mu004_muic_set_adcmode_oneshot(struct s2mu004_muic_data *muic_data);
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#endif /* !CONFIG_SEC_FACTORY */
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extern void s2mu004_hv_muic_adcmode_oneshot(struct s2mu004_muic_data *muic_data);
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#endif
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extern void s2mu004_muic_prepare_afc_charger(struct s2mu004_muic_data *muic_data);
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extern bool s2mu004_muic_check_change_dev_afc_charger
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(struct s2mu004_muic_data *muic_data, muic_attached_dev_t new_dev);
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#endif /* __S2MU004_MUIC_HV_H__ */
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