220 lines
6.6 KiB
C
220 lines
6.6 KiB
C
/*
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* s2mu106-muic-hv.h - MUIC for the Samsung s2mu004
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*
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* Copyright (C) 2018 Samsung Electrnoics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __S2MU106_MUIC_HV_H__
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#define __S2MU106_MUIC_HV_H__
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#define MUIC_HV_DEV_NAME "muic-s2mu106-hv"
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/* S2MU106 AFC INT MASK register(0x08) */
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#define INTMASK_VBADC_SHIFT 0
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#define INTMASK_VDNMON_SHIFT 1
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#define INTMASK_DNRES_SHIFT 2
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#define INTMASK_MPNACK_SHIFT 3
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#define INTMASK_MRXBUFOW_SHIFT 4
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#define INTMASK_MRXTRF_SHIFT 5
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#define INTMASK_MRXPERR_SHIFT 6
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#define INTMASK_MRXRDY_SHIFT 7
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#define INTMASK_VBADC_MASK (0x1 << INTMASK_VBADC_SHIFT)
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#define INTMASK_VDNMON_MASK (0x1 << INTMASK_VDNMON_SHIFT)
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#define INTMASK_DNRES_MASK (0x1 << INTMASK_DNRES_SHIFT)
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#define INTMASK_MPNACK_MASK (0x1 << INTMASK_MPNACK_SHIFT)
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#define INTMASK_MRXBUFOW_MASK (0x1 << INTMASK_MRXBUFOW_SHIFT)
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#define INTMASK_MRXTRF_MASK (0x1 << INTMASK_MRXTRF_SHIFT)
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#define INTMASK_MRXPERR_MASK (0x1 << INTMASK_MRXPERR_SHIFT)
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#define INTMASK_MRXRDY_MASK (0x1 << INTMASK_MRXRDY_SHIFT)
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/* S2MU106 AFC STATUS register(0x10) */
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#define STATUS_VBADC_SHIFT 0
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#define STATUS_VDNMON_SHIFT 4
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#define STATUS_DNRES_SHIFT 5
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#define STATUS_MPNACK_SHIFT 6
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#define STATUS_ADCEOC_SHIFT 7
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#define STATUS_VBADC_MASK (0xf << STATUS_VBADC_SHIFT)
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#define STATUS_VDNMON_MASK (0x1 << STATUS_VDNMON_SHIFT)
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#define STATUS_DNRES_MASK (0x1 << STATUS_DNRES_SHIFT)
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#define STATUS_MPNACK_MASK (0x1 << STATUS_MPNACK_SHIFT)
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#define STATUS_ADCEOC_MASK (0x1 << STATUS_ADCEOC_SHIFT)
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/* S2MU106 AFC CONTROL 1 register(0x2B) */
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#define AFCCTRL1_DPDNVDEN_SHIFT 0
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#define AFCCTRL1_DNVD_SHIFT 1
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#define AFCCTRL1_DPVD_SHIFT 3
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#define AFCCTRL1_VBUSADCEN_SHIFT 5
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#define AFCCTRL1_CTRLIDMON_SHIFT 6
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#define AFCCTRL1_AFCEN_SHIFT 7
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#define AFCCTRL1_DPDNVDEN_MASK (0x1 << AFCCTRL1_DPDNVDEN_SHIFT)
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#define AFCCTRL1_DNVD_MASK (0x3 << AFCCTRL1_DNVD_SHIFT)
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#define AFCCTRL1_DPVD_MASK (0x3 << AFCCTRL1_DPVD_SHIFT)
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#define AFCCTRL1_VBUSADCEN_MASK (0x1 << AFCCTRL1_VBUSADCEN_SHIFT)
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#define AFCCTRL1_CTRLIDMON_MASK (0x1 << AFCCTRL1_CTRLIDMON_SHIFT)
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#define AFCCTRL1_AFCEN_MASK (0x1 << AFCCTRL1_AFCEN_SHIFT)
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#define DPDN_HIZ (0x0)
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#define DPDN_GND (0x1)
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#define DPDN_0p6V (0x2)
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#define DPDN_3p3V (0x3)
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#define DP_HIZ_MASK (DPDN_HIZ << AFCCTRL1_DPVD_SHIFT)
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#define DP_GND_MASK (DPDN_GND << AFCCTRL1_DPVD_SHIFT)
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#define DP_0p6V_MASK (DPDN_0p6V << AFCCTRL1_DPVD_SHIFT)
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#define DP_3p3V_MASK (DPDN_3p3V << AFCCTRL1_DPVD_SHIFT)
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#define DN_HIZ_MASK (DPDN_HIZ << AFCCTRL1_DNVD_SHIFT)
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#define DN_GND_MASK (DPDN_GND << AFCCTRL1_DNVD_SHIFT)
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#define DN_0p6V_MASK (DPDN_0p6V << AFCCTRL1_DNVD_SHIFT)
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#define DN_3p3V_MASK (DPDN_3p3V << AFCCTRL1_DNVD_SHIFT)
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/* S2MU106 AFC CONTROL 2 register(0x2C) */
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#define AFCCTRL2_DP06EN_SHIFT 1
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#define AFCCTRL2_DNRESEN_SHIFT 2
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#define AFCCTRL2_MTXEN_SHIFT 3
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#define AFCCTRL2_MPING_SHIFT 4
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#define AFCCTRL2_RSTDM100UI_SHIFT 7
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#define AFCCTRL2_DP06EN_MASK (0x1 << AFCCTRL2_DP06EN_SHIFT)
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#define AFCCTRL2_DNRESEN_MASK (0x1 << AFCCTRL2_DNRESEN_SHIFT)
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#define AFCCTRL2_MTXEN_MASK (0x1 << AFCCTRL2_MTXEN_SHIFT)
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#define AFCCTRL2_MPING_MASK (0x1 << AFCCTRL2_MPING_SHIFT)
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#define AFCCTRL2_RSTDM100UI_MASK (0x1 << AFCCTRL2_RSTDM100UI_SHIFT)
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/* S2MU106 AFC OTP 6 register(0x2C) */
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#define AFCOTP6_CTRL_IDM_ON_REG_SEL_SHIFT 6
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#define AFCOTP6_CTRL_IDM_ON_REG_SEL_MASK (0x1 << AFCOTP6_CTRL_IDM_ON_REG_SEL_SHIFT)
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/* S2MU106 AFC TX BYTE DATA */
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#define AFCTXBYTE_VOL_SHIFT 4
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#define AFCTXBYTE_VOL_MASK (0xf << AFCTXBYTE_VOL_SHIFT)
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#define AFCTXBYTE_CUR_SHIFT 0
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#define AFCTXBYTE_CUR_MASK (0xf << AFCTXBYTE_CUR_SHIFT)
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#define AFCTXBYTE_5V 0x0
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#define AFCTXBYTE_6V 0x1
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#define AFCTXBYTE_7V 0x2
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#define AFCTXBYTE_8V 0x3
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#define AFCTXBYTE_9V 0x4
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#define AFCTXBYTE_10V 0x5
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#define AFCTXBYTE_11V 0x6
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#define AFCTXBYTE_12V 0x7
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#define AFCTXBYTE_13V 0x8
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#define AFCTXBYTE_14V 0x9
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#define AFCTXBYTE_15V 0xA
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#define AFCTXBYTE_16V 0xB
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#define AFCTXBYTE_17V 0xC
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#define AFCTXBYTE_18V 0xD
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#define AFCTXBYTE_19V 0xE
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#define AFCTXBYTE_20V 0xF
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#define AFCTXBYTE_0p75A 0x0
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#define AFCTXBYTE_0p90A 0x1
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#define AFCTXBYTE_1p05A 0x2
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#define AFCTXBYTE_1p20A 0x3
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#define AFCTXBYTE_1p35A 0x4
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#define AFCTXBYTE_1p50A 0x5
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#define AFCTXBYTE_1p65A 0x6
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#define AFCTXBYTE_1p80A 0x7
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#define AFCTXBYTE_1p95A 0x8
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#define AFCTXBYTE_2p10A 0x9
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#define AFCTXBYTE_2p25A 0xA
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#define AFCTXBYTE_2p40A 0xB
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#define AFCTXBYTE_2p55A 0xC
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#define AFCTXBYTE_2p70A 0xD
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#define AFCTXBYTE_2p85A 0xE
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#define AFCTXBYTE_3p00A 0xF
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/* S2MU004 HVRXBYTE register */
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#define HVRXBYTE_MAX 16
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/* S2MU004 AFC charger W/A Check NUM */
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#define AFC_CHARGER_WA_PING 5
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/* S2MU004 MPing miss SW Workaround - delay time */
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#define MPING_MISS_WA_TIME 2000
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#define AFC_MRXRDY_CNT_LIMIT (3)
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#define AFC_MPING_RETRY_CNT_LIMIT (20)
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#define AFC_QC_RETRY_CNT_LIMIT (3)
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#define VCHGIN_CHECK_CNT_LIMIT (3)
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#define IS_VCHGIN_9V(x) ((8000 <= x) && (x <= 10300))
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#define IS_VCHGIN_5V(x) ((4000 <= x) && (x <= 6000))
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typedef enum {
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MU106_IRQ_VDNMON = 1,
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MU106_IRQ_DNRES,
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MU106_IRQ_MPNACK,
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MU106_IRQ_MRXBUFOW,
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MU106_IRQ_MRXTRF,
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MU106_IRQ_MRXPERR,
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MU106_IRQ_MRXRDY = 7,
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MU106_IRQ_VCHGIN = 8,
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} afc_int_t;
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typedef enum {
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MU106_NOT_MASK = 0,
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MU106_MASK = 1,
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} int_mask_t;
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typedef enum {
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MU106_QC_PROTOCOL,
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MU106_AFC_PROTOCOL,
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} protocol_sw_t;
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typedef enum {
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QC_UNKHOWN,
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QC_5V,
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QC_9V,
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QC_12V,
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} qc_2p0_type_t;
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typedef enum {
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VDNMON_LOW = 0x00,
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VDNMON_HIGH = (0x1 << STATUS_VDNMON_SHIFT),
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VDNMON_DONTCARE = 0xff,
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} vdnmon_t;
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/* MUIC afc irq type */
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typedef enum {
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MUIC_AFC_IRQ_VDNMON = 0,
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MUIC_AFC_IRQ_MRXRDY,
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MUIC_AFC_IRQ_VBADC,
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MUIC_AFC_IRQ_MPNACK,
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MUIC_AFC_IRQ_DONTCARE = 0xff,
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} muic_afc_irq_t;
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typedef enum tx_data{
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MUIC_HV_5V = 0,
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MUIC_HV_9V,
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} muic_afc_txdata_t;
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struct s2mu106_muic_data;
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extern int s2mu106_hv_muic_init(struct s2mu106_muic_data *muic_data);
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extern void s2mu106_hv_muic_remove(struct s2mu106_muic_data *muic_data);
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extern muic_attached_dev_t hv_muic_check_id_err(struct s2mu106_muic_data *muic_data,
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muic_attached_dev_t new_dev);
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#ifdef CONFIG_HV_MUIC_VOLTAGE_CTRL
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extern int muic_afc_set_voltage(int vol);
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#endif
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#endif /* __S2MU106_MUIC_HV_H__ */
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