140 lines
3.4 KiB
C
140 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/sound/cs35l43.h -- Platform data for CS35L43
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*
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* Copyright (c) 2021 Cirrus Logic Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CS35L43_H
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#define __CS35L43_H
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#define CS35L43_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
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#define CS35L43_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE \
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| SNDRV_PCM_FMTBIT_S32_LE)
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#define CS35L43_VALID_PDATA 0x80000000
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#define CS35L43_NUM_DEFAULTS 41
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struct cs35l43_platform_data {
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bool gpio1_out_enable;
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bool gpio2_out_enable;
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bool classh_disable;
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bool dsp_ng_enable;
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bool vpbr_enable;
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int asp_sdout_hiz;
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int dsp_ng_pcm_thld;
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int dsp_ng_delay;
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int dout_hiz;
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int bst_vctrl;
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int bst_ipk;
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int hw_ng_sel;
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int hw_ng_delay;
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int hw_ng_thld;
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int gpio1_src_sel;
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int gpio2_src_sel;
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int vpbr_rel_rate;
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int vpbr_wait;
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int vpbr_atk_rate;
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int vpbr_atk_vol;
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int vpbr_max_att;
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int vpbr_thld;
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const char *dsp_part_name;
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const char *mfd_suffix;
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};
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struct cs35l43_pll_sysclk_config {
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int freq;
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int clk_cfg;
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};
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struct cs35l43_fs_mon_config {
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int freq;
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unsigned int fs1;
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unsigned int fs2;
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};
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extern const struct cs35l43_pll_sysclk_config cs35l43_pll_sysclk[64];
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extern const struct cs35l43_fs_mon_config cs35l43_fs_mon[7];
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extern const unsigned int cs35l43_hibernate_update_regs[CS35L43_POWER_SEQ_LENGTH];
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extern const u8 cs35l43_write_seq_op_sizes[CS35L43_POWER_SEQ_NUM_OPS][2];
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enum cs35l43_hibernate_state {
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CS35L43_HIBERNATE_AWAKE = 0,
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CS35L43_HIBERNATE_STANDBY = 1,
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CS35L43_HIBERNATE_UPDATE = 2,
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CS35L43_HIBERNATE_NOT_LOADED = 3,
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CS35L43_HIBERNATE_DISABLED = 4,
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};
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struct cs35l43_write_seq_elem {
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u8 size;
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u16 offset; /* offset in words from pseq_base */
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u8 operation;
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u32 *words;
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struct list_head list;
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};
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struct cs35l43_write_seq {
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const char *name;
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struct list_head list_head;
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unsigned int num_ops;
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unsigned int length;
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};
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enum cs35l43_hibernate_mode {
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CS35L43_ULTRASONIC_MODE_DISABLED = 0,
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CS35L43_ULTRASONIC_MODE_INBAND = 1,
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CS35L43_ULTRASONIC_MODE_OUT_OF_BAND = 2,
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};
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struct cs35l43_private {
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struct wm_adsp dsp; /* needs to be first member */
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struct snd_soc_component *component;
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struct cs35l43_platform_data pdata;
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struct device *dev;
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struct regmap *regmap;
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struct regulator_bulk_data supplies[2];
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int num_supplies;
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int irq;
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int extclk_cfg;
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int clk_id;
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int lrclk_fmt;
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int sclk_fmt;
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int asp_fmt;
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int hibernate_state;
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int hibernate_delay_ms;
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int ultrasonic_mode;
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int slot_width;
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int delta_requested;
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int delta_applied;
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unsigned int max_spi_freq;
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struct gpio_desc *reset_gpio;
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struct mutex hb_lock;
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struct mutex rate_lock;
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struct cs35l43_write_seq power_on_seq;
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void (*limit_spi_clock)(struct cs35l43_private *cs35l43, bool state);
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};
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int cs35l43_probe(struct cs35l43_private *cs35l43,
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struct cs35l43_platform_data *pdata);
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int cs35l43_remove(struct cs35l43_private *cs35l43);
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bool cs35l43_readable_reg(struct device *dev, unsigned int reg);
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bool cs35l43_precious_reg(struct device *dev, unsigned int reg);
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bool cs35l43_volatile_reg(struct device *dev, unsigned int reg);
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/* Power management */
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int cs35l43_suspend_runtime(struct device *dev);
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int cs35l43_resume_runtime(struct device *dev);
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extern const struct dev_pm_ops cs35l43_pm_ops;
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extern const struct reg_default cs35l43_reg[CS35L43_NUM_DEFAULTS];
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#endif /* __CS35L43_H */
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