134 lines
3 KiB
Plaintext
134 lines
3 KiB
Plaintext
Cadence DSI bridge
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==================
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The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
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Required properties:
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- compatible: should be set to "cdns,dsi".
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- reg: physical base address and length of the controller's registers.
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- interrupts: interrupt line connected to the DSI bridge.
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- clocks: DSI bridge clocks.
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- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
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- phys: phandle link to the MIPI D-PHY controller.
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- phy-names: must contain "dphy".
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- #address-cells: must be set to 1.
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- #size-cells: must be set to 0.
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Optional properties:
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- resets: DSI reset lines.
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- reset-names: can contain "dsi_p_rst".
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Required subnodes:
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- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
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2 ports are available:
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* port 0: this port is only needed if some of your DSI devices are
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controlled through an external bus like I2C or SPI. Can have at
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most 4 endpoints. The endpoint number is directly encoding the
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DSI virtual channel used by this device.
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* port 1: represents the DPI input.
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Other ports will be added later to support the new kind of inputs.
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- one subnode per DSI device connected on the DSI bus. Each DSI device should
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contain a reg property encoding its virtual channel.
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Cadence DPHY
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============
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Cadence DPHY block.
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Required properties:
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- compatible: should be set to "cdns,dphy".
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- reg: physical base address and length of the DPHY registers.
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- clocks: DPHY reference clocks.
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- clock-names: must contain "psm" and "pll_ref".
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- #phy-cells: must be set to 0.
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Example:
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dphy0: dphy@fd0e0000{
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compatible = "cdns,dphy";
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reg = <0x0 0xfd0e0000 0x0 0x1000>;
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clocks = <&psm_clk>, <&pll_ref_clk>;
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clock-names = "psm", "pll_ref";
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#phy-cells = <0>;
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};
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
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phys = <&dphy0>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi0_dpi_input: endpoint {
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remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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panel: dsi-dev@0 {
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compatible = "<vendor,panel>";
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reg = <0>;
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};
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};
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or
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
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phys = <&dphy1>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_panel_input>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_dpi_input: endpoint {
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remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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};
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i2c@xxx {
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panel: panel@59 {
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compatible = "<vendor,panel>";
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reg = <0x59>;
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port {
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dsi_panel_input: endpoint {
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remote-endpoint = <&dsi0_output>;
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};
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};
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};
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};
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