269 lines
8.1 KiB
Plaintext
269 lines
8.1 KiB
Plaintext
Altera SoCFPGA ECC Manager
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This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Cyclone5 and Arria5 ECC Manager
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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On Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-ocram-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- iram : phandle to On-Chip RAM definition.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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Example:
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eccmgr: eccmgr@ffd08140 {
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compatible = "altr,socfpga-ecc-manager";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l2-ecc@ffd08140 {
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compatible = "altr,socfpga-l2-ecc";
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reg = <0xffd08140 0x4>;
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interrupts = <0 36 1>, <0 37 1>;
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};
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ocram-ecc@ffd08144 {
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compatible = "altr,socfpga-ocram-ecc";
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reg = <0xffd08144 0x4>;
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iram = <&ocram>;
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interrupts = <0 178 1>, <0 179 1>;
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};
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};
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Arria10 SoCFPGA ECC Manager
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The Arria10 SoC ECC Manager handles the IRQs for each peripheral
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in a shared register instead of individual IRQs like the Cyclone5
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and Arria5. Therefore the device tree is different as well.
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ecc-manager"
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- altr,sysgr-syscon : phandle to Arria10 System Manager Block
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containing the ECC manager registers.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt.
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- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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- #interrupt-cells : must be set to 2.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Ethernet FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-eth-mac-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent Ethernet node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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NAND FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-nand-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent NAND node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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DMA FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-dma-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent DMA node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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USB FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-usb-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent USB node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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QSPI FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-qspi-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent QSPI node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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SDMMC FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-sdmmc-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent SD/MMC node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order for port A, and then single bit error interrupt,
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then double bit error interrupt in this order for port B.
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Example:
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eccmgr: eccmgr@ffd06000 {
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compatible = "altr,socfpga-a10-ecc-manager";
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altr,sysmgr-syscon = <&sysmgr>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
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<32 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
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<33 IRQ_TYPE_LEVEL_HIGH> ;
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};
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emac0-rx-ecc@ff8c0800 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0800 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
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<36 IRQ_TYPE_LEVEL_HIGH>;
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};
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emac0-tx-ecc@ff8c0c00 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0c00 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
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<37 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-buf-ecc@ff8c2000 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2000 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
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<43 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-rd-ecc@ff8c2400 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2400 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
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<45 IRQ_TYPE_LEVEL_HIGH>;
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};
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nand-wr-ecc@ff8c2800 {
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compatible = "altr,socfpga-nand-ecc";
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reg = <0xff8c2800 0x400>;
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altr,ecc-parent = <&nand>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
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<44 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma-ecc@ff8c8000 {
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compatible = "altr,socfpga-dma-ecc";
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reg = <0xff8c8000 0x400>;
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altr,ecc-parent = <&pdma>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
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<42 IRQ_TYPE_LEVEL_HIGH>;
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usb0-ecc@ff8c8800 {
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compatible = "altr,socfpga-usb-ecc";
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reg = <0xff8c8800 0x400>;
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altr,ecc-parent = <&usb0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
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<34 IRQ_TYPE_LEVEL_HIGH>;
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};
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qspi-ecc@ff8c8400 {
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compatible = "altr,socfpga-qspi-ecc";
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reg = <0xff8c8400 0x400>;
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altr,ecc-parent = <&qspi>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
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<46 IRQ_TYPE_LEVEL_HIGH>;
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};
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sdmmc-ecc@ff8c2c00 {
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compatible = "altr,socfpga-sdmmc-ecc";
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reg = <0xff8c2c00 0x400>;
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altr,ecc-parent = <&mmc>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<47 IRQ_TYPE_LEVEL_HIGH>,
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<16 IRQ_TYPE_LEVEL_HIGH>,
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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Stratix10 SoCFPGA ECC Manager
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The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
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in a shared register similar to the Arria10. However, ECC requires
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access to registers that can only be read from Secure Monitor with
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SMC calls. Therefore the device tree is slightly different.
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Required Properties:
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- compatible : Should be "altr,socfpga-s10-ecc-manager"
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt.
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- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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- #interrupt-cells : must be set to 2.
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Subcomponents:
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SDRAM ECC
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Required Properties:
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- compatible : Should be "altr,sdram-edac-s10"
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Example:
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eccmgr {
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compatible = "altr,socfpga-s10-ecc-manager";
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interrupts = <0 15 4>, <0 95 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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sdramedac {
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compatible = "altr,sdram-edac-s10";
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interrupts = <16 4>, <48 4>;
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};
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};
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