52 lines
2 KiB
Plaintext
52 lines
2 KiB
Plaintext
UniPhier GPIO controller
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Required properties:
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- compatible: Should be "socionext,uniphier-gpio".
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- reg: Specifies offset and length of the register set for the device.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Should be 2. The first cell is the pin number and the second
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cell is used to specify optional parameters.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
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The second cell bits[3:0] is used to specify trigger type as follows:
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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Valid combinations are 1, 2, 3, 4, 8.
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- ngpios: Specifies the number of GPIO lines.
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- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt)
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- socionext,interrupt-ranges: Specifies an interrupt number mapping between
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this GPIO controller and its interrupt parent, in the form of arbitrary
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number of <child-interrupt-base parent-interrupt-base length> triplets.
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Optional properties:
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- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt)
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Example:
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>;
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gpio-ranges-group-names = "gpio_range";
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ngpios = <248>;
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
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};
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Consumer Example:
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sdhci0_pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
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};
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Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document.
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Unfortunately, only the one's place is octal in the port numbering. (That is,
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PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper
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macro to calculate 29 * 8 + 4.
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