174 lines
5.4 KiB
Plaintext
174 lines
5.4 KiB
Plaintext
* ARM Generic Interrupt Controller, version 3
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AArch64 SMP cores are often associated with a GICv3, providing Private
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Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
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Software Generated Interrupts (SGI), and Locality-specific Peripheral
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Interrupts (LPI).
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Main node required properties:
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- compatible : should at least contain "arm,gic-v3".
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. Must be a single cell with a value of at least 3.
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If the system requires describing PPI affinity, then the value must
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be at least 4.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts. Other values are reserved for future use.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = edge triggered
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4 = level triggered
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The 4th cell is a phandle to a node describing a set of CPUs this
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interrupt is affine to. The interrupt must be a PPI, and the node
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pointed must be a subnode of the "ppi-partitions" subnode. For
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interrupt types other than PPI or PPIs that are not partitionned,
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this cell must be zero. See the "ppi-partitions" node description
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below.
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Cells 5 and beyond are reserved for future use and must have a value
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of 0 if present.
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- reg : Specifies base physical address(s) and size of the GIC
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registers, in the following order:
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- GIC Distributor interface (GICD)
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- GIC Redistributors (GICR), one range per redistributor region
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- GIC CPU interface (GICC)
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- GIC Hypervisor interface (GICH)
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- GIC Virtual CPU interface (GICV)
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GICC, GICH and GICV are optional.
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- interrupts : Interrupt source of the VGIC maintenance interrupt.
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Optional
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- redistributor-stride : If using padding pages, specifies the stride
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of consecutive redistributors. Must be a multiple of 64kB.
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- #redistributor-regions: The number of independent contiguous regions
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occupied by the redistributors. Required if more than one such
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region is present.
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- msi-controller: Boolean property. Identifies the node as an MSI
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controller. Only present if the Message Based Interrupt
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functionnality is being exposed by the HW, and the mbi-ranges
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property present.
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- mbi-ranges: A list of pairs <intid span>, where "intid" is the first
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SPI of a range that can be used an MBI, and "span" the size of that
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range. Multiple ranges can be provided. Requires "msi-controller" to
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be set.
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- mbi-alias: Address property. Base address of an alias of the GICD
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region containing only the {SET,CLR}SPI registers to be used if
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isolation is required, and if supported by the HW.
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Sub-nodes:
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PPI affinity can be expressed as a single "ppi-partitions" node,
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containing a set of sub-nodes, each with the following property:
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- affinity: Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.txt).
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GICv3 has one or more Interrupt Translation Services (ITS) that are
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used to route Message Signalled Interrupts (MSI) to the CPUs.
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These nodes must have the following properties:
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- compatible : Should at least contain "arm,gic-v3-its".
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- msi-controller : Boolean property. Identifies the node as an MSI controller
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- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
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which will generate the MSI.
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- reg: Specifies the base physical address and size of the ITS
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registers.
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Optional:
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- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
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address and size of the pre-ITS window.
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The main GIC node must contain the appropriate #address-cells,
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#size-cells and ranges properties for the reg property of all ITS
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nodes.
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Examples:
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gic: interrupt-controller@2cf00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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<0x0 0x2c000000 0 0x2000>, // GICC
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c020000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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msi-controller;
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mbi-ranges = <256 128>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c200000 0 0x20000>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride
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#redistributor-regions = <2>;
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reg = <0x0 0x2c010000 0 0x10000>, // GICD
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<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
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<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
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<0x0 0x2c040000 0 0x2000>, // GICC
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<0x0 0x2c060000 0 0x2000>, // GICH
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<0x0 0x2c080000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c200000 0 0x20000>;
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};
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gic-its@2c400000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c400000 0 0x20000>;
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};
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ppi-partitions {
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part0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu2>;
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};
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part1: interrupt-partition-1 {
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affinity = <&cpu1 &cpu3>;
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};
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};
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};
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device@0 {
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reg = <0 0 0 4>;
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interrupts = <1 1 4 &part0>;
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};
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