56 lines
1.9 KiB
Plaintext
56 lines
1.9 KiB
Plaintext
Broadcom BCM6345-style Level 1 interrupt controller
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This block is a first level interrupt controller that is typically connected
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directly to one of the HW INT lines on each CPU.
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Key elements of the hardware design include:
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- 32, 64 or 128 incoming level IRQ lines
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- Most onchip peripherals are wired directly to an L1 input
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- A separate instance of the register set for each CPU, allowing individual
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peripheral IRQs to be routed to any CPU
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- Contains one or more enable/status word pairs per CPU
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- No atomic set/clear operations
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- No polarity/level/edge settings
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- No FIFO or priority encoder logic; software is expected to read all
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2-4 status words to determine which IRQs are pending
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Required properties:
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- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
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- reg: specifies the base physical address and size of the registers;
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the number of supported IRQs is inferred from the size argument
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
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node; valid values depend on the type of parent interrupt controller
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If multiple reg ranges and interrupt-parent entries are present on an SMP
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system, the driver will allow IRQ SMP affinity to be set up through the
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/proc/irq/ interface. In the simplest possible configuration, only one
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reg range and one interrupt-parent is needed.
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The driver operates in native CPU endian by default, there is no support for
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specifying an alternative endianness.
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Example:
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periph_intc: interrupt-controller@10000000 {
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compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
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reg = <0x10000020 0x20>,
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<0x10000040 0x20>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>, <3>;
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};
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