32 lines
1 KiB
Plaintext
32 lines
1 KiB
Plaintext
Chips&Media Coda multi-standard codec IP
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========================================
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Coda codec IPs are present in i.MX SoCs in various versions,
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called VPU (Video Processing Unit).
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Required properties:
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- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
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(a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
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(b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
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(c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
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(d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
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- reg: should be register base and length as documented in the
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SoC reference manual
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- interrupts : Should contain the VPU interrupt. For CODA960,
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a second interrupt is needed for the MJPEG unit.
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- clocks : Should contain the ahb and per clocks, in the order
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determined by the clock-names property.
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- clock-names : Should be "ahb", "per"
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- iram : phandle pointing to the SRAM device node
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Example:
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vpu: vpu@63ff4000 {
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compatible = "fsl,imx53-vpu";
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reg = <0x63ff4000 0x1000>;
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interrupts = <9>;
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clocks = <&clks 63>, <&clks 63>;
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clock-names = "ahb", "per";
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iram = <&ocram>;
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};
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