88 lines
3.5 KiB
Plaintext
88 lines
3.5 KiB
Plaintext
MediaTek DWMAC glue layer controller
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This file documents platform glue layer for stmmac.
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Please see stmmac.txt for the other unchanged properties.
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The device node has following properties.
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Required properties:
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- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the MAC interrupts
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- interrupt-names: Should contain a list of interrupt names corresponding to
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the interrupts in the interrupts property, if available.
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Should be "macirq" for the main MAC IRQ
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- clocks: Must contain a phandle for each entry in clock-names.
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- clock-names: The name of the clock listed in the clocks property. These are
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"axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC
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- mac-address: See ethernet.txt in the same directory
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- phy-mode: See ethernet.txt in the same directory
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- mediatek,pericfg: A phandle to the syscon node that control ethernet
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interface and timing delay.
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Optional properties:
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- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
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It should be defined for rgmii/rgmii-rxid/mii interface.
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- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
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It should be defined for rgmii/rgmii-txid/mii/rmii interface.
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Both delay properties need to be a multiple of 170 for fine-tune rgmii,
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range 0~31*170.
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Both delay properties need to be a multiple of 550 for coarse-tune rgmii,
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range 0~31*550.
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Both delay properties need to be a multiple of 550 for mii/rmii,
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range 0~31*550.
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- mediatek,fine-tune: boolean property, if present indicates that fine delay
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is selected for rgmii interface.
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If present, tx-delay-ps/rx-delay-ps is 170+/-50ps per stage.
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Else tx-delay-ps/rx-delay-ps of coarse delay macro is 0.55+/-0.2ns per stage.
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This property do not apply to non-rgmii PHYs.
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Only coarse-tune delay is supported for mii/rmii PHYs.
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- mediatek,rmii-rxc: boolean property, if present indicates that the rmii
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reference clock, which is from external PHYs, is connected to RXC pin
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on MT2712 SoC.
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Otherwise, is connected to TXC pin.
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- mediatek,txc-inverse: boolean property, if present indicates that
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1. tx clock will be inversed in mii/rgmii case,
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2. tx clock inside MAC will be inversed relative to reference clock
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which is from external PHYs in rmii case, and it rarely happen.
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- mediatek,rxc-inverse: boolean property, if present indicates that
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1. rx clock will be inversed in mii/rgmii case.
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2. reference clock will be inversed when arrived at MAC in rmii case.
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- assigned-clocks: mac_main and ptp_ref clocks
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- assigned-clock-parents: parent clocks of the assigned clocks
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Example:
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eth: ethernet@1101c000 {
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compatible = "mediatek,mt2712-gmac";
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reg = <0 0x1101c000 0 0x1300>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq";
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phy-mode ="rgmii";
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mac-address = [00 55 7b b5 7d f7];
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clock-names = "axi",
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"apb",
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"mac_main",
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"ptp_ref",
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"ptp_top";
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clocks = <&pericfg CLK_PERI_GMAC>,
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<&pericfg CLK_PERI_GMAC_PCLK>,
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<&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>;
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assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
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<&topckgen CLK_TOP_APLL1_D3>;
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mediatek,pericfg = <&pericfg>;
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mediatek,tx-delay-ps = <1530>;
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mediatek,rx-delay-ps = <1530>;
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mediatek,fine-tune;
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mediatek,rmii-rxc;
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mediatek,txc-inverse;
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mediatek,rxc-inverse;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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};
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