86 lines
3 KiB
Plaintext
86 lines
3 KiB
Plaintext
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
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HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Additional properties are described here:
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Required properties
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- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
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- reg: Should contain rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"rc_dbi": controller configuration registers;
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"config": PCIe configuration space registers.
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- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
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- port-id: Should be 0, 1, 2 or 3.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if DMA operations are coherent.
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Hip05 Example (note that Hip06 is the same except compatible):
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pcie@b0080000 {
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compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
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reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
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reg-names = "rc_dbi", "config";
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bus-range = <0 15>;
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msi-parent = <&its_pcie>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
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num-lanes = <8>;
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port-id = <1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
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0x0 0 0 2 &mbigen_pcie 2 11
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0x0 0 0 3 &mbigen_pcie 3 12
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0x0 0 0 4 &mbigen_pcie 4 13>;
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};
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HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
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Some BIOSes place the host controller in a mode where it is ECAM
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compliant for all devices other than the root complex. In such cases,
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the host controller should be described as below.
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The properties and their meanings are identical to those described in
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host-generic-pci.txt except as listed below.
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Properties of the host controller node that differ from
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host-generic-pci.txt:
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- compatible : Must be "hisilicon,hip06-pcie-ecam", or
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"hisilicon,hip07-pcie-ecam"
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- reg : Two entries: First the ECAM configuration space for any
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other bus underneath the root bus. Second, the base
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and size of the HiSilicon host bridge registers include
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the RC's own config space.
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Example:
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pcie0: pcie@a0090000 {
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compatible = "hisilicon,hip06-pcie-ecam";
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reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */
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<0 0xa0090000 0 0x10000>; /* host bridge registers */
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bus-range = <0 31>;
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msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
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msi-map-mask = <0xffff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
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0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
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0x0 0 0 2 &mbigen_pcie0 650 4
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0x0 0 0 3 &mbigen_pcie0 650 4
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0x0 0 0 4 &mbigen_pcie0 650 4>;
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};
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