675 lines
20 KiB
Plaintext
675 lines
20 KiB
Plaintext
NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: Must be:
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- "nvidia,tegra20-pcie": for Tegra20
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- "nvidia,tegra30-pcie": for Tegra30
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- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
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- "nvidia,tegra210-pcie": for Tegra210
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- "nvidia,tegra186-pcie": for Tegra186
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- power-domains: To ungate power partition by BPMP powergate driver. Must
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contain BPMP phandle and PCIe power partition ID. This is required only
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for Tegra186.
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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- reg-names: Must include the following entries:
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"pads": PADS registers
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"afi": AFI registers
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"cs": configuration space region
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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- cell 0 specifies the bus and device numbers of the root port:
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[23:16]: bus number
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[15:11]: device number
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- cell 1 denotes the upper 32 address bits and should be 0
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- cell 2 contains the lower 32 address bits and is used to translate to the
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CPU address space
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- #size-cells: Size representation for root ports (must be 2)
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- ranges: Describes the translation of addresses for root ports and standard
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PCI regions. The entries must be 6 cells each, where the first three cells
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correspond to the address as described for the #address-cells property
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above, the fourth cell is the physical CPU address to translate to and the
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fifth and six cells are as described for the #size-cells property above.
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- The first two entries are expected to translate the addresses for the root
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port registers, which are referenced by the assigned-addresses property of
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the root port nodes (see below).
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- The remaining entries setup the mapping for the standard I/O, memory and
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prefetchable PCI regions. The first cell determines the type of region
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that is setup:
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- 0x81000000: I/O memory region
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- 0x82000000: non-prefetchable memory region
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- 0xc2000000: prefetchable memory region
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- #interrupt-cells: Size representation for interrupts (must be 1)
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- pex
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- afi
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- pll_e
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- cml (not required for Tegra20)
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- pex
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- afi
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- pcie_x
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Required properties on Tegra124 and later (deprecated):
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- phys: Must contain an entry for each entry in phy-names.
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- phy-names: Must include the following entries:
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- pcie
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These properties are deprecated in favour of per-lane PHYs define in each of
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the root ports (see below).
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Power supplies for Tegra20:
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- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
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supply 1.05 V.
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- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
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Power supplies for Tegra30:
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- Required:
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- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
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supply 1.05 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 3.3 V.
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- Optional:
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- If lanes 0 to 3 are used:
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- avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- If lanes 4 or 5 are used:
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- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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Power supplies for Tegra124:
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- Required:
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- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 3.3 V.
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- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
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Must supply 3.3 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 2.8-3.3 V.
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- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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Power supplies for Tegra210:
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- Required:
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- avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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- hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
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clocks. Must supply 1.8 V.
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- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
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Must supply 3.3 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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Power supplies for Tegra186:
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- Required:
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- dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
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supply 1.8 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 1.8 V.
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- vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
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supply 1.8 V.
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Root ports are defined as subnodes of the PCIe controller node.
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Required properties:
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- device_type: Must be "pci"
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- assigned-addresses: Address and size of the port configuration registers
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- reg: PCI bus address of the root port
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- #address-cells: Must be 3
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- #size-cells: Must be 2
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- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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property is sufficient.
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- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
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are:
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- Root port 0 uses 4 lanes, root port 1 is unused.
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- Both root ports use 2 lanes.
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Required properties for Tegra124 and later:
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in the nvidia,num-lanes property. Entries are of the form
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"pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
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Examples:
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=========
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Tegra20:
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--------
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SoC DTSI:
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pcie-controller@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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0x80003800 0x00000200 /* AFI registers */
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0x90000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <0 98 0x04 /* controller interrupt */
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0 99 0x04>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
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0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
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0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
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0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
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clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
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clock-names = "pex", "afi", "pll_e";
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resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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Board DTS:
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pcie-controller@80003000 {
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status = "okay";
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vdd-supply = <&pci_vdd_reg>;
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pex-clk-supply = <&pci_clk_reg>;
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/* root port 00:01.0 */
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pci@1,0 {
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status = "okay";
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/* bridge 01:00.0 (optional) */
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pci@0,0 {
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reg = <0x010000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* endpoint 02:00.0 */
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pci@0,0 {
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reg = <0x020000 0 0 0 0>;
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};
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};
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};
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};
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Note that devices on the PCI bus are dynamically discovered using PCI's bus
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enumeration and therefore don't need corresponding device nodes in DT. However
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if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
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device nodes need to be added in order to allow the bus' children to be
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instantiated at the proper location in the operating system's device tree (as
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illustrated by the optional nodes in the example above).
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Tegra30:
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--------
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SoC DTSI:
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pcie-controller@3000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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0x00003800 0x00000200 /* AFI registers */
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0x10000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
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0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
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clocks = <&tegra_car TEGRA30_CLK_PCIE>,
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<&tegra_car TEGRA30_CLK_AFI>,
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<&tegra_car TEGRA30_CLK_PLL_E>,
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<&tegra_car TEGRA30_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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Board DTS:
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pcie-controller@3000 {
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status = "okay";
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avdd-pexa-supply = <&ldo1_reg>;
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vdd-pexa-supply = <&ldo1_reg>;
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avdd-pexb-supply = <&ldo1_reg>;
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vdd-pexb-supply = <&ldo1_reg>;
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avdd-pex-pll-supply = <&ldo1_reg>;
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avdd-plle-supply = <&ldo1_reg>;
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vddio-pex-ctl-supply = <&sys_3v3_reg>;
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hvdd-pex-supply = <&sys_3v3_pexs_reg>;
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pci@1,0 {
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status = "okay";
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};
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pci@3,0 {
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status = "okay";
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};
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};
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Tegra124:
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---------
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SoC DTSI:
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pcie-controller@1003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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0x0 0x01003800 0x0 0x00000800 /* AFI registers */
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0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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<&tegra_car TEGRA124_CLK_AFI>,
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<&tegra_car TEGRA124_CLK_PLL_E>,
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<&tegra_car TEGRA124_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie-controller@1003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05_run>;
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dvddio-pex-supply = <&vdd_1v05_run>;
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avdd-pex-pll-supply = <&vdd_1v05_run>;
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hvdd-pex-supply = <&vdd_3v3_lp0>;
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hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
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vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
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avdd-pll-erefe-supply = <&avdd_1v05_run>;
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/* Mini PCIe */
|
|
pci@1,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
|
phy-names = "pcie-0";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Gigabit Ethernet */
|
|
pci@2,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
|
|
phy-names = "pcie-0";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
Tegra210:
|
|
---------
|
|
|
|
SoC DTSI:
|
|
|
|
pcie-controller@1003000 {
|
|
compatible = "nvidia,tegra210-pcie";
|
|
device_type = "pci";
|
|
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
|
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
|
|
0x0 0x02000000 0x0 0x10000000>; /* configuration space */
|
|
reg-names = "pads", "afi", "cs";
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
|
|
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
|
|
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
|
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
|
|
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
|
|
|
|
clocks = <&tegra_car TEGRA210_CLK_PCIE>,
|
|
<&tegra_car TEGRA210_CLK_AFI>,
|
|
<&tegra_car TEGRA210_CLK_PLL_E>,
|
|
<&tegra_car TEGRA210_CLK_CML0>;
|
|
clock-names = "pex", "afi", "pll_e", "cml";
|
|
resets = <&tegra_car 70>,
|
|
<&tegra_car 72>,
|
|
<&tegra_car 74>;
|
|
reset-names = "pex", "afi", "pcie_x";
|
|
status = "disabled";
|
|
|
|
pci@1,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
|
reg = <0x000800 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <4>;
|
|
};
|
|
|
|
pci@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
|
reg = <0x001000 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <1>;
|
|
};
|
|
};
|
|
|
|
Board DTS:
|
|
|
|
pcie-controller@1003000 {
|
|
status = "okay";
|
|
|
|
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
|
|
hvddio-pex-supply = <&vdd_1v8>;
|
|
dvddio-pex-supply = <&vdd_pex_1v05>;
|
|
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
|
|
hvdd-pex-pll-e-supply = <&vdd_1v8>;
|
|
vddio-pex-ctl-supply = <&vdd_1v8>;
|
|
|
|
pci@1,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
|
|
phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
|
|
status = "okay";
|
|
};
|
|
|
|
pci@2,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
|
phy-names = "pcie-0";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
Tegra186:
|
|
---------
|
|
|
|
SoC DTSI:
|
|
|
|
pcie@10003000 {
|
|
compatible = "nvidia,tegra186-pcie";
|
|
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
|
|
device_type = "pci";
|
|
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
|
|
0x0 0x10003800 0x0 0x00000800 /* AFI registers */
|
|
0x0 0x40000000 0x0 0x10000000>; /* configuration space */
|
|
reg-names = "pads", "afi", "cs";
|
|
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
|
|
0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
|
|
0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
|
|
0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
|
0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
|
|
0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
|
|
|
|
clocks = <&bpmp TEGRA186_CLK_AFI>,
|
|
<&bpmp TEGRA186_CLK_PCIE>,
|
|
<&bpmp TEGRA186_CLK_PLLE>;
|
|
clock-names = "afi", "pex", "pll_e";
|
|
|
|
resets = <&bpmp TEGRA186_RESET_AFI>,
|
|
<&bpmp TEGRA186_RESET_PCIE>,
|
|
<&bpmp TEGRA186_RESET_PCIEXCLK>;
|
|
reset-names = "afi", "pex", "pcie_x";
|
|
|
|
status = "disabled";
|
|
|
|
pci@1,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
|
|
reg = <0x000800 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <2>;
|
|
};
|
|
|
|
pci@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
|
|
reg = <0x001000 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <1>;
|
|
};
|
|
|
|
pci@3,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
|
|
reg = <0x001800 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <1>;
|
|
};
|
|
};
|
|
|
|
Board DTS:
|
|
|
|
pcie@10003000 {
|
|
status = "okay";
|
|
|
|
dvdd-pex-supply = <&vdd_pex>;
|
|
hvdd-pex-pll-supply = <&vdd_1v8>;
|
|
hvdd-pex-supply = <&vdd_1v8>;
|
|
vddio-pexctl-aud-supply = <&vdd_1v8>;
|
|
|
|
pci@1,0 {
|
|
nvidia,num-lanes = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
pci@2,0 {
|
|
nvidia,num-lanes = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pci@3,0 {
|
|
nvidia,num-lanes = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|