65 lines
2.6 KiB
Plaintext
65 lines
2.6 KiB
Plaintext
* Renesas R-Car PCIe interface
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Required properties:
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compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
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"renesas,pcie-r8a7779" for the R8A7779 SoC;
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"renesas,pcie-r8a7790" for the R8A7790 SoC;
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"renesas,pcie-r8a7791" for the R8A7791 SoC;
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"renesas,pcie-r8a7793" for the R8A7793 SoC;
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"renesas,pcie-r8a7795" for the R8A7795 SoC;
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"renesas,pcie-r8a7796" for the R8A7796 SoC;
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"renesas,pcie-r8a77980" for the R8A77980 SoC;
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"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
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RZ/G1 compatible device.
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"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: base address and length of the PCIe controller registers.
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- bus-range: PCI bus numbers covered
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions.
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- dma-ranges: ranges for the inbound memory regions.
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- interrupts: two interrupt sources for MSI interrupts, followed by interrupt
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source for hardware related interrupts (e.g. link speed change).
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt numbers.
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- clocks: from common clock binding: clock specifiers for the PCIe controller
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and PCIe bus clocks.
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- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
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Optional properties:
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- phys: from common PHY binding: PHY phandle and specifier (only make sense
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for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
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- phy-names: from common PHY binding: should be "pcie".
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Example:
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SoC-specific DT Entry:
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
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0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
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0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
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0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
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0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 116 4>;
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clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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};
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