150 lines
4.5 KiB
Plaintext
150 lines
4.5 KiB
Plaintext
Mediatek MMDVFS driver binding
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=========================================
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The Mediatek MMDVFS(Multimedia Dynamic Voltage and Frequency Scaling) driver
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is used to set clk for Mediatek multimedia hardwares, such as display, camera,
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mdp and video codec. MMDVFS driver reads which clock muxes and clock sources
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are used on this platform from DTS, and set current clock according to current
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voltage changed by dvfsrc_vcore.
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Required properties:
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- compatible : shall contain "mediatek,mmdvfs".
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- operating-points-v2: contains any one of opp tables for multimedia modules.
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MMDVFS uses it to get voltage setting on this platform.
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- mediatek,support_mux: contains a list of clock mux names defined
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in clock-names.
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- mediatek,mux_*: a series of properties with mediatek,mux_ prefix.
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Each property represents one clock mux, and its value is a
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list of all the clock sources for it. The postfix * and every
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item in the property must be from the clock-names.
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- clock, clock-names: list all clock muxes and clock sources for multimedia
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hardwares.
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Optional properties:
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If the platform needs frequency hopping for some clock sources, these following
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properties should be set.
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- mediatek,support_hopping: a list of clock names supporting frequency hopping.
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- mediatek,hopping_*: a cell with the same size as opp numbers of an opp table
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for any MM module and each entry represents the clock
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rate for each opp. For example, the first entry is the
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clock rate set in opp-0, and the second entry is the
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clock rate set in opp-1.
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- mediatek,action: a cell with one entry.
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It represents the action taken when setting clocks.
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0 or this property is not set:
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Do not set frequency hopping and just set clock mux.
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1:
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If the voltage is increasing, set frequency hopping
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first. If the voltage is decreasing, set clock mux
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first.
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Example:
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opp_table_mm: opp-table-mm {
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compatible = "operating-points-v2";
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opp-0 {
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opp-hz = /bits/ 64 <315000000>;
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opp-microvolt = <650000>;
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};
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opp-1 {
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opp-hz = /bits/ 64 <450000000>;
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opp-microvolt = <725000>;
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};
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opp-2 {
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opp-hz = /bits/ 64 <606000000>;
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opp-microvolt = <825000>;
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};
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};
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opp_table_cam: opp-table-cam {
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compatible = "operating-points-v2";
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opp-0 {
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opp-hz = /bits/ 64 <315000000>;
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opp-microvolt = <650000>;
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};
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opp-1 {
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opp-hz = /bits/ 64 <416000000>;
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opp-microvolt = <725000>;
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};
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opp-2 {
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opp-hz = /bits/ 64 <560000000>;
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opp-microvolt = <825000>;
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};
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};
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.... /* Other opp tables for multimedia modules */
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mmdvfs {
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compatible = "mediatek,mmdvfs";
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operating-points-v2 = <&opp_table_mm>;
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mediatek,support_mux = "mm", "cam", "img", "ipe",
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"venc", "vdec", "dpe", "ccu";
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mediatek,mux_mm = "clk_mmpll_d5_d2",
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"clk_mmpll_d7", "clk_tvdpll_mainpll_d2_ck";
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mediatek,mux_cam = "clk_mmpll_d5_d2",
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"clk_univpll_d3", "clk_adsppll_d5";
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mediatek,mux_img = "clk_mmpll_d5_d2",
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"clk_univpll_d3", "clk_tvdpll_mainpll_d2_ck";
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mediatek,mux_ipe = "clk_mmpll_d5_d2",
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"clk_univpll_d3", "clk_mainpll_d2";
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mediatek,mux_venc = "clk_mainpll_d3",
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"clk_mmpll_d7", "clk_mmpll_d5";
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mediatek,mux_vdec = "clk_univpll_d2_d2",
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"clk_univpll_d3", "clk_univpll_d2";
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mediatek,mux_dpe = "clk_mainpll_d3",
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"clk_mmpll_d7", "clk_mainpll_d2";
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mediatek,mux_ccu = "clk_mmpll_d5_d2",
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"clk_univpll_d3", "clk_adsppll_d5";
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mediatek,support_hopping = "clk_mmpll_ck";
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mediatek,hopping_clk_mmpll_ck = <630000000 630000000 650000000>;
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mediatek,action = <1>;
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clocks = <&topckgen CLK_TOP_MM>,
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<&topckgen CLK_TOP_CAM>,
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<&topckgen CLK_TOP_IMG>,
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<&topckgen CLK_TOP_IPE>,
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<&topckgen CLK_TOP_VENC>,
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<&topckgen CLK_TOP_VDEC>,
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<&topckgen CLK_TOP_DPE>,
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<&topckgen CLK_TOP_CCU>,
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<&topckgen CLK_TOP_MMPLL_D5>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_TVDPLL_MAINPLL_D2_CK>,
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<&topckgen CLK_TOP_ADSPPLL_D5>,
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<&topckgen CLK_TOP_MAINPLL_D2>,
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<&topckgen CLK_TOP_MMPLL_D6>,
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<&topckgen CLK_TOP_MMPLL_D7>,
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<&topckgen CLK_TOP_UNIVPLL_D3>,
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<&topckgen CLK_TOP_MAINPLL_D3>,
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<&topckgen CLK_TOP_MMPLL_D5_D2>,
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<&topckgen CLK_TOP_UNIVPLL_D2_D2>,
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<&topckgen CLK_TOP_MMPLL_CK>;
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clock-names = "mm",
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"cam",
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"img",
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"ipe",
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"venc",
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"vdec",
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"dpe",
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"ccu",
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"clk_mmpll_d5",
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"clk_univpll_d2",
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"clk_tvdpll_mainpll_d2_ck",
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"clk_adsppll_d5",
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"clk_mainpll_d2",
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"clk_mmpll_d6",
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"clk_mmpll_d7",
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"clk_univpll_d3",
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"clk_mainpll_d3",
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"clk_mmpll_d5_d2",
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"clk_univpll_d2_d2",
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"clk_mmpll_ck";
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};
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